- 您现在的位置：买卖IC网 > PDF目录220054 > TLC320AC02CPM (TEXAS INSTRUMENTS INC) SPECIALTY ANALOG CIRCUIT, PQFP64 PDF资料下载
参数资料
| 型号： | TLC320AC02CPM |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封装： | PLASTIC, QFP-64 |
| 文件页数： | 19/86页 |
| 文件大小： | 471K |
| 代理商： | TLC320AC02CPM |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页
2–12
2.14.1.2 Frame-Sync Delayed (FSD), Master Mode
For the master, the frame-sync delayed output occurs 1/2 shift-clock period ahead of FS to compensate for
the time delay through the master and slave devices. The timing relationships are as follows:
1.
When the FSD register data is 0, then FSD goes low on the falling edge of SCLK prior to the rising
edge of SCLK when FS goes low (see Figure 4 – 4).
2.
When the FSD register data is greater than 17, then FSD goes low on a rising edge of SCLK that
is the FSD register number of SCLKs after the falling edge of FS.
Register data values from 1 to 17 should not be used.
2.14.1.3 Frame Sync (FS), Slave Mode
The frame-sync timing is generated externally, applied to FS, and controls the ADC and DAC timing (see
Subsection 2.15.4). The external frame-sync width must be a minimum of one shift clock to be recognized
and can remain low until the next data frame is required.
2.14.1.4 Frame-Sync Delayed (FSD), Slave Mode
This output is fed from the master to the first slave and the first slave FSD output to the second and so on
down the chain. The FSD timing sequence in the slave mode is as follows:
1.
When the FSD register data is 0, then FSD goes low after FS goes low (see Figure 4 – 5).
2.
When the FSD register data is greater than 17, FSD goes low on a rising edge of SCLK that is
the FSD register number of SCLKs after the falling edge of FS.
Data values from 1 to 17 should not be used.
2.14.2
Data Out (DOUT)
DOUT is placed in the high-impedance state on the seventeenth rising edge of SCLK (internal or external)
after the falling edge of frame sync. In the primary communication, the data word is the ADC conversion
result. In the secondary communication, the data is the register read results when requested by the
read/write (R/W) bit with the eight MSBs set to 0 (see Section 2.16). If no register read is requested, the
secondary word is all zeroes.
2.14.2.1 Data Out, Master Mode
In the master mode, DOUT is taken from the high-impedance state by the falling edge of frame sync. The
most significant data bit then appears on DOUT.
2.14.2.2 Data Out, Slave Mode
In the slave mode, DOUT is taken from the high-impedance state by the falling edge of the external frame
sync or the rising edge of the external SCLK, whichever occurs first (see Figure 4 – 7). The falling edge of
frame sync can occur
±1/4 SCLK period around the SCLK rising edge (see Figure 4–3). The most
significant data bit then appears on DOUT.
2.14.3
Data In (DIN)
In the primary communication, the data word is the digital input signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function
(see Section 2.16).
2.14.4
Hardware Program Terminals (FC1 and FC0)
These inputs provide for hardware programming requests for secondary communication or phase
adjustment. These inputs work in conjunction with the control bits D01 and D00 of the primary data word
or control bits DS15 and DS14 of the secondary data word. The data on FC1 and FC0 are latched on the
rising edge of the next internally generated primary or secondary frame-sync interval. These inputs should
be tied low if not used (see Section 2.17 and Table 2–3).
相关PDF资料 |
PDF描述 |
|---|---|
| TL431N | 1-OUTPUT THREE TERM VOLTAGE REFERENCE, PDIP8 |
| TPS658620ZQZT | 11-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA120 |
| TPS40211DGQ | 0.4 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO10 |
| TC126331 | 0.4 A SWITCHING REGULATOR, 115 kHz SWITCHING FREQ-MAX, PDSO5 |
| TC126331TR | 0.4 A SWITCHING REGULATOR, 115 kHz SWITCHING FREQ-MAX, PDSO5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLC320AC02I | 制造商:TI 制造商全称:Texas Instruments 功能描述:Single-Supply Analog Interface Circuit |
| TLC320AC02IFN | 功能描述:接口—CODEC SNGL CH Codec Bandwidth Indpendent RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLC320AC02IFNR | 功能描述:接口—CODEC SNGL CH Codec Bandwidth Indpendent RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLC320AC02IPM | 功能描述:接口—CODEC SNGL CH Codec Bandwidth Indpendent RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLC320AC03CFNG4 | 制造商:Texas Instruments 功能描述: |
发布紧急采购，3分钟左右您将得到回复。