参数资料
型号: TLE6266G
厂商: INFINEON TECHNOLOGIES AG
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封装: 18 MM, PLASTIC, SOP-28
文件页数: 9/50页
文件大小: 1020K
代理商: TLE6266G
Datasheet TLE 6266 G
Version 2.21
17
July 29th, 2005
The transmission cycle begins when the chip is selected by the chip select not input CSN
(H to L). After the CSN input returns from L to H, the word that has been read in becomes
the new control word. The DO output switches to tristate status at this point, thereby
releasing the DO bus for other usage.
The state of DI is shifted into the input register with every falling edge on CLK. The state
of DO is shifted out of the output register after every rising edge on CLK. For more details
of the SPI timing please refer to Figure 11 to 15.
CAN Bus Wiring Failure direct Read-out
The SPI output bit 0 for CAN bus wiring failure can be read out without SPI transmission
directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal from LOW to
HIGH resets the SPI diagnosis bit 0.
Table 6
SPI Input Data Protocol
Table 7
SPI Output Data Protocol
IBIT
Input Data
OBIT Output Data
15
Disable 3V Reset Comparator
15
Thermal Shutdown Transceiver
14
not used
14
Thermal Shutdown Switches
13
Cyclic Wake Time Bit2
13
CAN Failure 2 and 4
12
Cyclic Wake Time Bit1
12
CAN Failure 1 and 3a
11
PWM Enable HS1
11
CAN Failure 6
10
Mode 1
10
CAN Failure 6a
9
Mode 0
9
CAN Failure 5 and 7
8
not used
8
CAN Failure 3
7
Supervisor Enable
7
3V Supervisor (HIGH = Vcc > 3V)
6
LS-Switch 2
6
Status LS2
5
LS-Switch 1
5
Status LS1
4
Timebase Test
4
Temperature Prewarning for all
Switches
3
HS-Switch 3
3
Vs Undervoltage Lockout
2
HS-Switch 2
2
Window Watchdog Reset
1
HS-Switch 1
1
Overcurrent HS1
0
Watchdog Trigger
0
CAN Bus Failure
H=ON
L=OFF
H=ON
L=OFF
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