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| 型号： | TLE7242-2G |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | GREEN, PLASTIC, DSO-28 |
| 文件页数： | 8/50页 |
| 文件大小： | 1210K |
| 代理商： | TLE7242-2G |
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TLE7242-2G
Functional Description and Electrical Characteristics
Data Sheet
16
Rev. 1.0, 2008-07-09
Figure 10
Phase Synchronization Diagram
The TEST pin is an input pin that is used during IC level test. This pin should be connected directly to ground for
normal device operation.
The FAULT pin is an open drain output pin. This pin will be pulled low by the device when an unmasked fault has
been detected. The fault masks are programmed via SPI message #7.
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V,
T
j = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
5.3
Diagnostics
The TLE7242 2G includes both on-state and off-state diagnostics. On-state diagnostics are active when the OUTx
pin is driven high and off-state diagnostics are active when the OUTx pin is driven low. A detected fault can be
used to activate the open drain FAULT pin on the IC. This pin can be used to interrupt the microcontroller when a
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
5.2.1
Logic input low voltage
V
ILMAX
––0.8
V
5.2.2
Logic input high voltage
V
IHMIN
2.0
–
V
5.2.3
Logic output low voltage
V
OLMAX
––0.2
V
I
L=200A
5.2.4
Logic output high voltage
V
OHMIN
0.8*V_
SIGNAL
––
V
I
L=-200A
5.2.5
Pull down digital input (SI, CLK,
SCK, PHASE_SYNC, ENABLE,
TEST)
I
pd
10
–
50
A
V
in=V_SIGNAL
(current drain to
ground)
5.2.6
Pull up digital input (CS_B,
RESET_B)
I
pu
-10
–
-50
A
V
in=0V (Current
drain from
V_SIGNAL)
5.2.7
Fault Pin voltage
V
fault
–
0.4
V
Active state;
I
fault=2mA
5.2.8
CLK high time (rise 2.0V to fall
2.0V)
t
14
8––
ns
5.2.9
CLK low time (fall 0.8V to rise 0.8V)
t
15
8––
ns
OUTx
PWM/32 CLK
PHASE_SYNC
T1
gate turns off
on-time cut
short
normal
turn off
time
Programmed delay =
8/32 PWM periods
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