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参数资料
| 型号： | TLV1543CDBR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封装： | GREEN, PLASTIC, SSOP-20 |
| 文件页数： | 2/29页 |
| 文件大小： | 804K |
| 代理商： | TLV1543CDBR |
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TLV1543C, TLV1543I, TLV1543M
3.3V 10BIT ANALOGTODIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS072E DECEMBER 1992 REVISED JANUARY 2004
10
WWW.TI.COM
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 3 V to 5.5 V, I/O CLOCK frequency = 1.1 MHz for the TLV1543C, and TLV1543I
VCC = Vref+ = 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz for the TLV1543M
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Linearity error (see Note 6)
±1
LSB
Zero error (see Note 7)
±1
LSB
Full-scale error (see Note 7)
±1
LSB
Total unadjusted error (see Note 8)
±1
LSB
ADDRESS = 1011
512
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1100
0
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1101
1023
tc(1)
Conversion time
See Figures 9 14
21
s
tc(2)
Total cycle time (access, sample, and conversion)
See Figures 9 14
and Note 10
21
+10 I/O
CLOCK
periods
s
t(acq)
Channel acquisition time (sample)
See Figures 9 14
and Note 10
6
I/O
CLOCK
periods
tv
Valid time, DATA OUT remains valid after I/O CLOCK
↓
See Figure 6
10
ns
td(I/O-DATA)
Delay time, I/O CLOCK
↓ to DATA OUT valid
See Figure 6
240
ns
td(I/O-EOC)
Delay time, tenth I/O CLOCK
↓ to EOC↓
See Figure 7
70
240
ns
td(EOC-DATA) Delay time, EOC↑ to DATA OUT (MSB)
See Figure 8
100
ns
tPZH, tPZL
Enable time, CS
↓ to DATA OUT (MSB driven)
See Figure 3
1.3
s
tPHZ, tPLZ
Disable time, CS
↑ to DATA OUT (high impedance)
See Figure 3
150
ns
tr(EOC)
Rise time, EOC
See Figure 8
300
ns
tf(EOC)
Fall time, EOC
See Figure 7
300
ns
tr(bus)
Rise time, data bus
See Figure 6
300
ns
tf(bus)
Fall time, data bus
See Figure 6
300
ns
td(I/O-CS)
Delay time, tenth I/O CLOCK
↓ to CS↓ to abort conversion
(see Note 11)
9
s
All typical values are at TA = 25°C.
NOTES:
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6).
11. Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock
(1.425
s) after the transition.
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