参数资料
型号: TLV1548CDBRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
封装: GREEN, PLASTIC, SSOP-20
文件页数: 24/37页
文件大小: 693K
代理商: TLV1548CDBRG4
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATIONS INFORMATION
simplified analog input analysis
Using the equivalent circuit in Figure 33, the time required to charge the analog input capacitance from 0 to VS
within 1/2 LSB can be derived as follows:
The capacitance charging voltage is given by:
where
Rt = Rs + ri
tc = Cycle time
V
C +
V
S
1–e
–tc RtCi
The input impedance Zi is 1 k at 5 V, and is higher (~ 5 k) at 2.7 V. The final voltage to 1/2 LSB is given by:
VC (1/2 LSB) = VS – (VS/2048)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
and time to change to 1/2 LSB (minimum sampling time) is:
tch (1/2 LSB) = Rt × Ci × ln(2048)
V
S *
V
S
2048
+ V
S
1–e
–tc RtCi
where
ln(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
tch (1/2 LSB) = (Rs + 1 k) × 55 pF × ln(2048)
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x I/O CLK.
tch (1/2 LSB) ≤ 6x 1/fI/O
Therefore the maximum I/O CLK frequency is:
max(fI/O) = 6/tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci)
(1)
(2)
(3)
(4)
(5)
(6)
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