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参数资料
| 型号： | TLV320ADC3001IYZHR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PBGA16 |
| 封装： | GREEN, DSBGA-16 |
| 文件页数： | 9/81页 |
| 文件大小： | 836K |
| 代理商： | TLV320ADC3001IYZHR |
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WCLK
BCLK
DOUT
‘0’
R-2
2
1
0
X
R-1
X
1/fs
FrameTime/2
DOUT_Tristate
BCLK
WCLK
DIN/
DOUT
n-1 n-2
1
0
n-1 n-2
1
0
1/fs
LSB
MSB
LeftChannel
RightChannel
n-3
2
n-3
LSB
MSB
SLAS548C
– OCTOBER 2008 – REVISED APRIL 2011
Figure 15. First Channel Disabled, Second Channel Enabled, Hi-Z State Enabled
The sync signal for the ADC filter is not generated based on the disabled channel. The sync signal for the filter
corresponds to the beginning of the earlier of the two channels. If the first channel is disabled, the filter sync is
generated at the beginning of the second channel, if it is enabled. If both the channels are disabled, there is no
output to the serial bus, and the filter sync corresponds to the beginning of the frame.
By default, when the word clocks and bit clocks are generated by the TLV320ADC3001, these clocks are active
only when the ADC is powered up within the device. This is done to save power. However, it also supports a
feature wherein both the word clocks and bit clocks can be active even when the codec in the device is powered
down. This is useful when using the TDM mode with multiple codecs on the same bus or when word clocks or bit
clocks are used in the system as general-purpose clocks.
Right-Justified Mode
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock. See Figure 16 for right-justifed mode timing.
Figure 16. Timing Diagram for Right-Justified Mode
For right-justified mode, the number of bit clocks per frame should be greater than twice the programmed word
length of the data. Note that the time-slot-based mode is not available in the right-justified mode.
Left-Justified Mode
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock. Figure 17 shows the standard timing of the left-justified mode.
Copyright
2008–2011, Texas Instruments Incorporated
17
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