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参数资料
| 型号： | TLV320AIC26IRHBR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 13/67页 |
| 文件大小： | 883K |
| 代理商： | TLV320AIC26IRHBR |
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TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
20
D When PLL is enabled and D = 0, the following condition must be satisfied
80 MHz
v MCLK
K
P
v 110 MHz
2MHz
v MCLK
P
v 20 MHz
4
v J v 55
D When PLL is enabled and D ≠ 0, the following condition must be satisfied
80 MHz
v MCLK
K
P
v 110 MHz
10 MHz
v MCLK
P
v 20 MHz
4
v J v 11
Example 1:
For MCLK = 12 MHz and Fsref = 44.1 kHz
P = 1, K = 7.5264
J = 7, D = 5264
Example 2:
For MCLK = 12 MHz and Fsref = 48.0 kHz
P = 1, K = 8.192
J = 8, D = 1920
MONO AUDIO ADC
Analog Front End
The analog front end of the audio ADC consists of an analog MUX and a programmable gain amplifier (PGA). The MUX
can connect either the MICIN or AUX signal through the PGA to the ADC for audio recording. The ’AIC26 also has an option
of choosing both MICIN and AUX as a differential input pair. The ’AIC26 also includes a microphone bias circuit, which can
source up to 4.7-mA current and is programmable to a 2-V or 2.5-V level. The bias block is powered down when both the
ADC and analog mixer blocks are powered down.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for
analog antialiasing filtering are very relaxed. The ’AIC26 integrates a second order analog antialiasing filter with 20-dB
attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides sufficient antialiasing filtering without
requiring any external components.
The PGA allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with
an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC
output samples, depending on the register programming. This soft-stepping ensures that volume control changes occur
smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power down, the PGA
soft-steps the volume to mute before shutting down. A read-only flag (D0 control register 04H/Page2) is set whenever the
gain applied by PGA equals the desired value set by the register. The softstepping control can be disabled by
programming D15=1 in register 1DH of Page02. When soft-stepping is enabled, the MCLK signal to the device should not
be changed until the ADC power-down flag is set. When the flag is set, the internal soft-stepping process and power-down
sequence is complete, and the MCLK can be stopped if desired.
Delta-Sigma ADC
The analog-to-digital converter is a delta-sigma modulator with 128 times oversampling ratio. The ADC can support a
maximum output rate of 53 kHz.
Decimation Filter
The audio ADC includes an integrated digital decimation filter that removes high-frequency content and downsamples the
audio data from an initial sampling rate of 128 times Fs to the final output sampling rate of Fs. The decimation filter provides
a linear phase output response with a group delay of 17/Fs. The 3-dB bandwidth of the decimation filter extends to 0.45
Fs and scales with the sample rate (Fs)
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相关代理商/技术参数 |
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| TLV320AIC26IRHBRG4 | 功能描述:接口—CODEC Lo-Pwr Stereo Codec RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC27 | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
| TLV320AIC27CPFB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLV320AIC27IPFB | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
| TLV320AIC27PFB | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
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