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参数资料
| 型号： | TLV320AIC26IRHBR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封装： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 21/67页 |
| 文件大小： | 883K |
| 代理商： | TLV320AIC26IRHBR |
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TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
28
In a third programmable configuration, the ’AIC26 can be programmed to monitor and automatically power down the audio
output drivers upon detection of a short-circuit condition (Page2, REG1DH, bit D7), in addition to setting the short-circuit
flag in Page2, REG1DH, bitD6. When the device has detected a short and resulted in this condition, the short-circuit flag
is cleared when all the routings to the speaker driver are disabled (i.e., DAC, Analog Mixer, and Keyclick blocks are powered
down by user).
AUDIO OUTPUT DRIVER POWER-ON POP REDUCTION SCHEME
The ’AIC26 implements a pop reduction scheme to reduce audible artifacts during power up and power down of the audio
output drivers. This scheme can be controlled by programming bits D2 and D1 of REG1EH/Page2. By default, the driver
pop reduction scheme is enabled and can be disabled by programming bit D2 of Reg1EH/Page2 to 1. When this scheme
is enabled and the virtual ground connection is not used (VGND amplifier is powered down), the audio output driver slowly
charges up any external ac-coupling capacitors to reduce audible artifacts. Bit D1 of REG1EH/Page2 provides control of
the charging time for the ac-coupling capacitor as either 0.8 sec or 4 sec. When the virtual ground amplifier is powered up
and used, the external ac-coupling capacitor is eliminated, and the power up time becomes 1 ms. This scheme takes effect
whenever the audio output drivers are powered up due to enabling any of the DAC, the Analog Mixer, or the Keyclick
Generator.
Pop Reduction for DAC Routing
Whenever the audio DAC is powered on or off, a slight change in the output dc offset voltage may occur and can be heard
as a weak pop in the output. In order to reduce this artifact, the ’AIC26 implements a DAC pop reduction scheme, which
is programmable using bits D5D2 in REG1DH/Page2. Bit D5 enables the scheme, which implements a slow transition
between the starting dc level and the final dc level. For best results, program bits D4D2 in REG1DH/Page2 to 100.
AUDIO MIXING
Digital Sidetone
The digital sidetone control attenuates the output from the ADCs decimation filter and routes its output to be mixed with
the DAC digital input. If bit D7 of REG03H/Page2 is reset, the output of the sidetone control is mixed with the stereo DAC
input. Care must be taken while selecting the digital sidetone gain so that the output of the digital mixer is not overloaded.
The digital sidetone block implements gains from 0 dB to –48 dB in steps of 1.5 dB. Gain changes are implemented at
zero-crossings of the signal to avoid any audible artifacts. The digital sidetone block is automatically internally disabled
if ADC and DAC are operating at different sampling rates, or if the DAC is powered down.
Analog Mixer
The analog mixer can be used to route the analog input selected for the ADC (MICIN or AUX) through an analog volume
control and then mix it with the audio DAC output. The analog mixer feature is available only if single-ended MICIN or AUX
is selected as the input to the ADC, not when the ADC input is configured in fully-differential mode. This feature is available
even if the ADC and DAC are powered down. The analog volume control in this path has a gain range from 12 dB to
–34.5 dB in 0.5-dB steps plus mute and includes soft-stepping logic. The internal oscillator is used for soft-stepping
whenever the ADC and DAC are powered down.
KEYCLICK
A special circuit has been included for inserting a squarewave signal into the analog output signal path based on register
control. This functionality is intended for generating keyclick sounds for user feedback. Register 04H/Page2 contains bits
that control the amplitude, frequency, and duration of the square-wave signal. The frequency of the signal can be varied
from 62.5 Hz to 8 kHz and its duration can be programmed from 2 periods to 32 periods. Whenever this register is written,
the square-wave is generated and coupled into the audio output, going to both audio outputs. The keyclick enable bit D15
of control register 04H/Page2 is reset after the duration of keyclick is played out. This capability is available even when
the ADC and DAC are powered down.
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相关代理商/技术参数 |
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| TLV320AIC26IRHBRG4 | 功能描述:接口—CODEC Lo-Pwr Stereo Codec RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC27 | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
| TLV320AIC27CPFB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLV320AIC27IPFB | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
| TLV320AIC27PFB | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
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