参数资料
型号: TLV320AIC32IRHBR
厂商: TEXAS INSTRUMENTS INC
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封装: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件页数: 42/80页
文件大小: 1270K
代理商: TLV320AIC32IRHBR
www.ti.com ............................................................................................................................................. SLAS479C – AUGUST 2005 – REVISED DECEMBER 2008
Page 0 / Register 22:
LINE1R to Right ADC Control Register (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D1–D0
R/W
00
Right ADC PGA Soft-Stepping Control
00: Right ADC PGA soft-stepping at once per Fs
01: Right ADC PGA soft-stepping at once per two Fs
10-11: Right ADC PGA soft-stepping is disabled
Page 0 / Register 23:
LINE2R to Right ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Reserved. Write only zero to this bit.
D6–D3
R/W
1111
LINE2R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2R to the right ADC PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = -–1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001-1110: Reserved. Do not write these sequences to these register bits
1111: LINE2R is not connected to the right ADC PGA
D2
R/W
0
Right ADC Channel Weak Common-Mode Bias Control
0:
Right ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
1:
Right ADC channel unselected inputs are biased weakly to the ADC common- mode voltage
D1–D0
R
00
Reserved. Write only zeros to these register bits
Page 0 / Register 24:
LINE1L to Right ADC Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Reserved. Write Only zero to this bit.
D6–D3
R/W
1111
LINE1L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the right ADC PGA
D2–D0
R
000
Reserved. Write only zeros to these register bits.
Page 0 / Register 25:
MICBIAS Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0 V
10: MICBIAS output is powered to 2.5 V
11: MICBIAS output is connected to AVDD
D5–D3
R
000
Reserved. Write only zeros to these register bits.
D2–D0
R
XXX
Reserved. Write only zeros to these register bits.
Copyright 2005–2008, Texas Instruments Incorporated
47
Product Folder Link(s): TLV320AIC32
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