参数资料
型号: TLV70018QDDCRQ1
厂商: Texas Instruments
文件页数: 2/19页
文件大小: 0K
描述: IC REG LDO 1.8V .2A SOT23-5
标准包装: 3,000
稳压器拓扑结构: 正,固定式
输出电压: 1.8V
输入电压: 2 V ~ 5.5 V
稳压器数量: 1
电流 - 输出: 200mA(最小值)
电流 - 限制(最小): 320mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-5 细型,TSOT-23-5
供应商设备封装: 5-SOT
包装: 带卷 (TR)

TLV70018-Q1
SLVSB67A – NOVEMBER 2011 – REVISED MARCH 2012
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
T A
–40°C to 125°C
PACKAGE
5 Pin DDC, SOT23 Reel of 3000
ORDERABLE PART NUMBER
TLV70018QDDCRQ1
TLV70040QDDCRQ1
TLV70012QDDCRQ1
TOP SIDE MAKING
DAL
Preview
SDO
(1)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperatur e range (unless otherwise noted) (1)
VALUE
MIN
MAX
UNIT
IN
–0.3
+6.0
V
Voltage
(2)
EN
OUT
–0.3
–0.3
+6.0
+6.0
V
V
Current (source)
Output short-circuit duration
OUT
Internally Limited
Indefinite
Temperature
Electrostatic Discharge Rating
Operating virtual junction, T J
Storage, T stg
Human Body Model (HBM) AEC-Q100 Classification Level H2
Charged Device Model (CDM) AEC-Q100 Classification Level
C3B
–55
–55
+150
+150
2
750
°C
°C
kV
V
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
All voltages are with respect to network ground terminal.
DISSIPATION RATINGS
DERATING
PACKAG
FACTOR ABOVE
BOARD
Low-K (1)
E
DDC
R θ JC
90°C/W
R θ JA
280°C/W
T A = 25°C
3.6 mW/°C
T A ≤ 25°C
360 mW
T A = 70°C
200 mW
T A = 85°C
145 mW
T A = 125°C
51 mW
High-K
(2)
DDC
90°C/W
200°C/W
5.0 mW/°C
500 mW
275 mW
200 mW
106 mW
(1)
(2)
The JEDEC low-K (1s) board used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the
board.
The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2
Product Folder Link(s): TLV70012-Q1
Copyright ? 2011–2012, Texas Instruments Incorporated
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