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参数资料
| 型号： | TM128160CKFWG |
| 厂商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SPECIFICATION FOR LCD MODULE |
| 中文描述： | 规格液晶模块 |
| 文件页数： | 13/26页 |
| 文件大小： | 290K |
| 代理商： | TM128160CKFWG |
12/25
6.4 Instruction code
Instruction List
Upper Code
Lower Code
Reg.
No.
Register
Name
R/
W
RS
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
DB
0
Description
Exe
cu-
tion
Cyc
le
IR
Index
0
0
*
*
*
*
*
*
*
*
*
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Sets the index register value.
0
Note1
SR
Status read
1
0
L7
L6
L5
L4
L3
L2
L1
L0
0
C6
C5
C4
C3
C2
C1
C0
Reads the driving raster-row
position (L7–0) and contrast setting
(C6–0).
0
R00h
Start
oscillation
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
Starts the oscillation mode.
10
ms
Note1
Device
code read
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
Reads 0766H.
0
R01h
Driver
output
control
0
1
0
0
0
0
0
0
CM
S
SGS
0
0
0
NL4
NL3
NL2
NL1
NL0 Sets the common driver shift
direction (CMS), segment driver
shift direction (SGS) and driving
duty ratio (NL4–0).
0
R02h
LCD-
driving-
waveform
control
0
1
0
0
0
0
0
RST
B/C
EOR
0
0
NW
5
NW
4
NW
3
NW
2
NW
1
NW
0
Sets LCD drive AC waveform
(B/C), and EOR output (EOR) or the
number of n-raster-rows (NW5–0)
at C-pattern AC drive.
0
R03h
Power
control 1
0
1
BS3
BS2
BS1
BS0
BT3
BT2
BT1
BT0
0
DC2
DC1
DC0
AP1
AP0
SLP
STB
Sets the sleep mode (SLP), standby
mode (STB), LCD power on (AP1–
0), boosting cycle (DC2–0),
boosting output multiplying factor
(BT2–0), operation of voltage
inverting circuit (BT3) and LCD
drive bias value (BS3–0).
0
R04h
Contrast
control
0
1
0
0
0
0
0
VR2
VR1
VR0
0
CT6
CT5
CT4
CT3
CT2
CT1
CT0
Sets the regulator adjustment (VR2–
0) and contrast adjustment (CT6–0).
0
R05h
Entry mode
0
1
SPR
0
0
0
0
0
HWM
0
0
0
I/D1
I/D0
AM
LG2
LG1
LG0 Specifies AC counter mode (AM),
increment/decrement mode (I/D1–
0), high-speed write mode (HWM).
0
Note2
R06h
Compare
Resister
0
1
CP1
5
CP1
4
CP1
3
CP1
2
CP1
1
CP1
0
CP9
CP8
CP7
CP6
CP5
CP4
CP3
CP2
CP1
CP0
Specifies the compare resister
(CP15-0),
0
R07h
Display
control
0
1
0
0
0
0
0
VLE2
VLE1
SPT
0
0
0
0
B/W REV
D1
D0
Specifies display on (D1-0), black-
and-white reversed display (REV),
pixel on/off mode (ALB), screen
division driving (SPT) and vertical
scroll .(VLE2-1)
0
R0Bh Frame
frequency
control
0
1
0
0
0
0
0
0
DIV
1
DIV
0
0
0
0
0
RTN
3
RTN
2
RTN
1
RTN
0
Specifies the line retrace period
(RTN3–0) and operating clock
frequency division ratio (DIV1–0).
0
R0Ch Power
control 2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
VC2
VC1
VC0 Sets the adjustment factor for the
Vci voltage (VC2–0).
0
R11h
Vertical
scroll
control
0
1
VL2
7
VL2
6
VL2
5
VL2
4
VL2
3
VL2
2
VL2
1
VL2
0
VL1
7
VL1
6
VL1
5
VL1
4
VL1
3
VL1
2
VL1
1
VL1
0
Sets the 1
st
screen display start
raster- row (VL17-10) and 2
nd
screen display start raster-row
(VL27-20).
0
R14h
1
st
screen
driving
position
0
1
SE
17
SE
16
SE
15
SE
14
SE
13
SE
12
SE
11
SE
10
SS
17
SS
16
SS
15
SS
14
SS
13
SS
12
SS
11
SS
10
Sets the 1
st
screen driving start
position (SS17–10) and 1
st
screen
driving end position (SE17–10).
0
R15h
2
nd
screen
driving
position
0
1
SE
27
SE
26
SE
25
SE
24
SE
23
SE
22
SE
21
SE
20
SS
27
SS
26
SS
25
SS
24
SS
23
SS
22
SS
21
SS
20
Sets 2
nd
screen driving start position
(SS27–20) and 2
nd
screen driving
end position (SE27–20).
0
R16h
Horizontal
RAM
address
position
0
1
HE
A7
HEA
6
HEA
5
HEA
4
HEA
3
HEA
2
HEA
1
HEA
0
HSA
7
HSA
6
HSA
5
HSA
4
HSA
3
HSA
2
HSA
1
HSA
0
Sets start (HSA7–0) and end
(HEA7–0) of the horizontal RAM
address range.
0
R17h
Vertical
RAM
address
position
0
1
VEA
7
VEA
6
VEA
5
VEA
4
VEA
3
VEA
2
VEA
1
VEA
0
VSA
7
VSA
6
VSA
5
VSA
4
VSA
3
VSA
2
VSA
1
VSA
0
Sets start (VSA7–0) and end
(VEA7–0) of the vertical RAM
address range.
0
R20h
RAM write
data mask
0
1
WM
15
WM
14
WM
13
WM
12
WM
11
WM
10
WM
9
WM
8
WM
7
WM
6
WM
5
WM
4
WM
3
WM
2
WM
1
WM
0
Specifies write data mask (WM15–
0) at RAM write.
0
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