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参数资料
| 型号： | TMP86C847UG |
| 厂商： | Toshiba Corporation |
| 英文描述： | Zener Diode; Application: General; Pd (mW): 500; Vz (V): 15.7 to 16.5; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35 |
| 中文描述： | 8位微控制器 |
| 文件页数： | 115/160页 |
| 文件大小： | 1541K |
| 代理商： | TMP86C847UG |
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Page 107
TMP86C847UG
(2)
LSB receive mode
LSB receive mode is selected by setting SIOCR1<SIODIR> to “1”, in which case the data is
received sequentially beginning with the least significant bit (Bit0).
10.3.2.3 Transmit/receive mode
(1)
MSB transmit/receive mode
MSB transmit/receive mode are selected by setting SIOCR1<SIODIR> to “0” in which case the
data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received
sequentially beginning with the most significant (Bit7).
(2)
LSB transmit/receive mode
LSB transmit/receive mode are selected by setting SIOCR1<SIODIR> to “1”, in which case the
data is transferred sequentially beginning with the least significant bit (Bit0) and the data is received
sequentially beginning with the least significant (Bit0).
10.3.3 Transfer modes
Transmit, receive and transmit/receive mode are selected by using SIOCR1<SIOM>.
10.3.3.1 Transmit mode
Transmit mode is selected by writing “00B” to SIOCR1<SIOM>.
(1)
Starting the transmit operation
Transmit mode is selected by setting “00B” to SIOCR1<SIOM>. Serial clock is selected by using
SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>.
When a transmit data is written to the transmit buffer register (SIOTDB), SIOSR<TXF> is cleared
to “0”.
After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to “1” the falling edge of
SCK
pin.
The data is transferred sequentially starting from SO pin with the direction of the bit specified by
SIOCR1<SIODIR>, synchronizing with the
SCK
pin's falling edge.
SIOSR<SEF> is kept in high level, between the first clock falling edge of
SCK
pin and eighth
clock falling edge.
SIOSR<TXF> is set to “1” at the rising edge of pin after the data written to the SIOTDB is trans-
ferred to shift register, then the INTSIO interrupt request is generated, synchronizing with the next
falling edge on
SCK
pin.
Note 1: In internal clock operation, when SIOCR1<SIOS> is set to "1", transfer mode does not start
without writing a transmit data to the transmit buffer register (SIOTDB).
Note 2: In internal clock operation, when the SIOCR1<SIOS> is set to "1", SIOTDB is transferred to shift
register after maximum 1-cycle of serial clock frequency, then a serial clock is output from
SCK
pin.
Note 3: In external clock operation, when the falling edge is input from
SCK
pin after SIOCR1<SIOS> is
set to "1", SIOTDB is transferred to shift register immediately.
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