参数资料
型号: TMP86FS49BUG
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-64
文件页数: 22/54页
文件大小: 2519K
代理商: TMP86FS49BUG
Page 12
2. Operational Description
2.2 System Clock Controller
TMP86FS49BUG
2.2.2 Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock
2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
2.2.2.1 Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
Figure 2-4 Configuration of Timing Generator
Multi-
plexer
High-frequency
clock fc
Low-frequency
clock fs
Divider
SYSCK
fc/4
fc or fs
Machine cycle counters
Main system clock generator
1
2
1
4
3
2
8
7
10
9
12
11
14
13
16
15
DV7CK
Multiplexer
Warm-up
controller
Watchdog
timer
A
S
B
Y
S
B0
A0 Y0
B1
A1 Y1
5
6
17 18 19 20 21
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
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相关代理商/技术参数
参数描述
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