Interrupts
7-18
Internal interrupts operate in a similar manner. In the IIF register, the bit corre-
sponding to an internal interrupt (e.g., TINT0, TINT1) can be read and written
to through software. Writing a 1 sets the interrupt latch, and writing a 0 clears
it. All internal interrupts are one H1/H3 cycle in length. If any previous bit values
of the IIF register need to be preserved, a modification to IIF should be per-
formed with logic operations (AND, OR, etc), directly to the IIF register.
Figure 7–3.IIF Register Modification
correct
LDI @MASK,R0
AND R0, IIF
incorrect
LDI IIF, R1
AND @MASK, R1
LDI R1, IIF
7.4.3
Interrupt Processing
For an interrupt to occur, at least two conditions must be met:
All interrupts must be enabled globally by setting the GIE bit to 0 in the CPU
status register (ST).
The interrupt must be enabled by setting the corresponding bit in the IIE
register.
The CPU interrupt processing cycle (shown in Figure 7–4) involves several
events. The corresponding interrupt flag in the IIF register is cleared, the val-
ues of the GIE and CF status register bits are preserved, the cache is frozen
(CF = 1), interrupts are globally disabled (GIE = 0), and the CPU completes
all fetched instructions. Then, the interrupt vector is fetched and loaded into
the PC, and the CPU continues execution of the first instruction in the interrupt
service routine (ISR). When you use RETIcondor RETIcondD to return from
the interrupt service routine, the previous GIE and CF bit values are recovered.
If you wish to make the interrupt service routine interruptible, you can set the
GIE bit to 1 after entering the ISR. In addition, you can enable the cache. Be
aware that because the PGIE and PCF status register bits are one deep, they
preserve only the previous GIE and CF bits.
Note:
The GIE, and CF are preserved and loaded with new values after the
completion of the last instruction that was fetched before the interrupt was
flushed. This guarantees later restoration of correct flag values.