Coordinating Communication Ports With the CPU and DMA Coprocessor
12-17
Communication Ports
12.6 Coordinating Communication Ports With the CPU and DMA Coprocessor
The communication ports support synchronization with two types of signals:
A ready/not ready signal that can halt CPU and DMA accesses to a com-
munication port
Interrupts that can be used to signal the CPU and DMA
The simplest form of synchronization is based on a ready/not-ready signal. If
the DMA or CPU attempt to read an empty input FIFO or write to a full output
FIFO, a not-ready signal is returned, and the DMA or CPU continues to read
or write (halting the peripheral bus) until a ready signal is received. The ready
signal for the output channel is OCRDY (output channel ready), which is also
an interrupt signal. The ready signal for the input channel is ICRDY (input
channel ready), which is also an interrupt signal.
In the interrupt form of synchronization, each communication port generates
four different interrupt signals, as listed below (interrupt vector locations for
these are shown in Figure 7–2):
ICFULL (input channel full): indicates that the input FIFO has eight words.
ICRDY (input channel ready): indicates that at least one word is in the input
FIFO.
OCRDY (output channel ready): indicates that at least one word space is
available in the output FIFO.
OCEMPTY (output channel empty): Indicates that the output FIFO is
empty.
The CPU can respond to all four of these interrupt signals. The DMA coproces-
sor can respond only to the ICRDY and OCRDY interrupt signals. Each DMA
channel can respond only to the ICRDY and OCRDY signals coming from its
own communication port; that is, DMA channel ican synchronize only with
ICRDYiand OCRDYi
Notice that none of the four communication-port interrupt signals has flags in
the IIF register. These four communication-port status signals (ICFULL,
ICRDY, OCRDY, and OCEMPTY) can be obtained by checking the input and
output levels in the communication port control register (CPCR) with logical
instructions. For example, to poll for an ICFULL condition, bit 12 can be tested
for a bit value equal to 1. See subsection 12.3.1, Communication-Port Control
Register (CPCR) on page 12-8, for more information about checking for
communication-port conditions.