Clocking of Memory Accesses
8-20
8.4.2
Data Loads and Stores
Four types of instructions perform loads, memory reads, and stores: two-oper-
and instructions, three-operand instructions, multiplier/ALU operation with
store instructions, and parallel multiply and add instructions. See Chapter 6 for
detailed information on addressing modes.
As discussed in Chapter 9, the number of bus cycles for external memory
accesses differs in some cases from the number of CPU execution cycles. For
external reads, the number of bus cycles and CPU execution cycles is identi-
cal. For external writes, there are always at least two bus cycles, but unless
there is a port access conflict, there is only one CPU execution cycle. In the
following examples, any difference in the number of bus cycles and CPU
cycles is noted.
8.4.2.1
Two-Operand Instruction Memory Accesses
Figure 8–2.Two-Operand Instruction Word
31
0 X 0
Operation
dst(src)
G
src(dst)
24 23
16 15
8 7
0
Two-operand instructions include all those instructions with bits 31–29 being
000
2
or 010
2
(see Figure 8–2). In the case of a data read, bits 15–0 represent
the srcoperand. Internal data reads are always performed during H1. External
data reads always start at the beginning of H3 with the address presented on
the external bus, and they complete with the latching of the data word at the
end of H1.
In the case of a data store, bits 15–0 represent the dst operand. Internal data
stores are performed during H3. External data stores always start at the
beginning of H3 with the address and data presented on the external bus.
8.4.2.2
Three-Operand Instruction Memory Reads
Figure 8–3.Three-Operand Instruction Word
Operation
31
0 0 1
2423
16
8
7
0
15
dst
T
src2
src1
Three-operand instructions include all instructions with bits 31–29 being 001
2
(see Figure 8–3). The source operands, src1and src2 come from either regis-
ters or memory. When one or more of the source operands are from memory,
these instructions are always memory reads.
If only one of the source operands is from memory (either src1or src2) and is
located in internal memory, the data is read during H1. If the single memory