参数资料
型号: TMS470R1A384PZ-T
厂商: Texas Instruments
文件页数: 30/62页
文件大小: 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
标准包装: 90
系列: TMS470
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 48MHz
连通性: CAN,C2Slb,I²C,SCI,SPI
外围设备: DMA,PWM,WDT
输入/输出数: 53
程序存储器容量: 384KB(384K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.71 V ~ 2.05 V
数据转换器: A/D 12x10b
振荡器型: 外部
工作温度: -40°C ~ 105°C
封装/外壳: 100-LQFP
包装: 托盘
产品目录页面: 718 (CN2011-ZH PDF)
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
其它名称: 296-19292
ZPLL AND CLOCK SPECIFICATIONS
Timing Requirements for ZPLL Circuits Enabled or Disabled
Switching Characteristics Over Recommended Operating Conditions for Clocks
(1) (2)
SPNS110E – AUGUST 2005 – REVISED MAY 2008 ......................................................................................................................................................... www.ti.com
MIN
TYP
MAX UNIT
f(OSC)
Input clock frequency
4
20 MHz
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
OSC FAIL frequency(1)
53
kHz
(1)
Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1)
bits equal to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
PARAMETER
TEST CONDITIONS(3)
MIN
MAX
UNIT
Pipeline mode enabled
48
MHz
f(SYS)
System clock frequency(4)
Pipeline mode disabled
24
MHz
f(CONFIG)
System clock frequency - flash config mode
24
MHz
f(ICLK)
Interface clock frequency
24
MHz
f(ECLK)
External clock output frequency for ECP module
24
MHz
Pipeline mode enabled
20.8
ns
tc(SYS)
Cycle time, system clock
Pipeline mode disabled
41.6
ns
tc(CONFIG)
Cycle time, system clock - flash config mode
41.6
ns
tc(ICLK)
Cycle time, interface clock
41.6
ns
tc(ECLK)
Cycle time, ECP module external clock output
41.6
ns
(1)
f(SYS) = M × f(OSC)/R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the
CLKDIVPRE [2:0] bits in the global control register (GLBCTRL[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the
GLBCTRL register (GLBCTRL.3).
f(SYS) = f(OSC)/R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS)/X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1]
bits in the SYS module.
(2)
f(ECLK) = f(ICLK)/N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
(3)
Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
(4)
Flash Vread must be set to 5 V to achieve maximum system clock frequency.
36
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TMS470R1A384
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