参数资料
型号: TMS470R1A384PZ-T
厂商: Texas Instruments
文件页数: 40/62页
文件大小: 0K
描述: IC RISC MCU 384K FLASH 100-LQFP
标准包装: 90
系列: TMS470
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 48MHz
连通性: CAN,C2Slb,I²C,SCI,SPI
外围设备: DMA,PWM,WDT
输入/输出数: 53
程序存储器容量: 384KB(384K x 8)
程序存储器类型: 闪存
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.71 V ~ 2.05 V
数据转换器: A/D 12x10b
振荡器型: 外部
工作温度: -40°C ~ 105°C
封装/外壳: 100-LQFP
包装: 托盘
产品目录页面: 718 (CN2011-ZH PDF)
配用: 296-23003-ND - KIT DEV KICKSTART TMS470
其它名称: 296-19292
SPIn Slave Mode External Timing Parameters
Data Valid
SPInSIMO
SPInSOMI
SPInCLK
(clock polarity = 1)
SPInCLK
(clock polarity = 0)
SPISIMO Data Must
Be Valid
SPISOMI Data Is Valid
1
2
3
4
5
6
7
www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
(CLOCK PHASE = 1, SPInCLK = input, SPInSIMO = input, and SPInSOMI = output)
(1) (2) (3) (4) (see Figure 16)
NO.
MIN
MAX
UNIT
1
tc(SPC)S
Cycle time, SPInCLK(5)
100
256tc(ICLK)
ns
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
2(6)
ns
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
3(6)
ns
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S - 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
Valid time, SPInCLK high after SPInSOMI data valid
tv(SOMI-SPCH)S
0.5tc(SPC)S - 6 - tr
(clock polarity = 0)
4(6)
ns
Valid time, SPInCLK low after SPInSOMI data valid
tv(SOMI-SPCL)S
0.5tc(SPC)S - 6 - tf
(clock polarity = 1)
Valid time, SPInSOMI data valid after SPInCLK high
tv(SPCH-SOMI)S
0.5tc(SPC)S - 6 - tr
(clock polarity = 0)
5(6)
ns
Valid time, SPInSOMI data valid after SPInCLK low
tv(SPCL-SOMI)S
0.5tc(SPC)S - 6 - tf
(clock polarity = 1)
Setup time, SPInSIMO before SPInCLK high
tsu(SIMO-SPCH)S
6
(clock polarity = 0)
6(6)
ns
Setup time, SPInSIMO before SPInCLK low
tsu(SIMO-SPCL)S
6
(clock polarity = 1)
Valid time, SPInSIMO data valid after SPInCLK high
tv(SPCH-SIMO)S
6
(clock polarity = 0)
7(6)
ns
Valid time, SPInSIMO data valid after SPInCLK low
tv(SPCL-SIMO)S
6
(clock polarity = 1)
(1)
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
(2)
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1[12:5].
(3)
For rise and fall timings, see the "Switching Characteristics for Output Timings versus Load Capacitance" table.
(4)
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
(5)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1[12:5] register bits.
For PS values of 0: tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
(6)
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2[1]).
Figure 16. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Copyright 2005–2008, Texas Instruments Incorporated
45
Product Folder Link(s): TMS470R1A384
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