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参数资料
| 型号： | TMS57014ADWBLE |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | DUAL, SERIAL INPUT LOADING, 18-BIT DAC, PDSO28 |
| 封装： | PLASTIC, SOIC-28 |
| 文件页数： | 12/17页 |
| 文件大小： | 250K |
| 代理商： | TMS57014ADWBLE |
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reset / initialization (continued)
120 Cycles of Fs
5 periods max
INIT
Internal
Reset
LRCK
Figure 1. Reset Timing Relationships
timing and control
The timing and control circuit generates and distributes necessary clocks throughout this design. XIN is the
external master clock input. The sample rate of the data paths is set as LRCK = XIN/512. With a fixed
oversampling ratio of 32x and each PWM output value requiring 16 XIN cycles, the effect of changing XIN is
shown in Table 1.
The DAC can be operated at any conversion rate between 48 kHz and 32 kHz by choosing the appropriate
master-clock frequency. Some of the functions of the converter, such as the de-emphasis filter, operate only
at the frequencies in Table 1.
Table 1. Master Clock to Sample Rate Comparison
XIN
(MHz)
256FSO
(MHz)
LRCK
(kHz)
24.5760
12.2880
48.0
22.5792
11.2896
44.1
19.3536
9.6768
37.8
16.3840
8.1920
32.0
digital-audio data interface
The conversion cycle is synchronized to the rising edge of LRCK, and the data must meet the setup
requirements specified in the timing requirements table. The input data is 16 or 18 bits with the MSB or LSB
first as selected in the system register. The BCK frequency must be equal to or greater than 32 Fs for 16-bit data
or 36 Fs for 18-bit data where Fs is the sample rate. Figure 2 illustrates the input timing.
15
14
1
0
15
14
1
0
15
14
1
0
15
14
1
0
17
16
Right Channel
Left Channel
BCK
DATA
(16-bit)
DATA
(18-bit)
LRCK
17
16
Figure 2. Audio-Data Input Timing
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