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参数资料
| 型号： | TMS57014ADWBLE |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | DUAL, SERIAL INPUT LOADING, 18-BIT DAC, PDSO28 |
| 封装： | PLASTIC, SOIC-28 |
| 文件页数： | 13/17页 |
| 文件大小： | 250K |
| 代理商： | TMS57014ADWBLE |
TMS57014A
DUAL AUDIO DIGITAL-TO-ANALOG CONVERTER
SLAS077D – SEPTEMBER 1993 – REVISED NOVEMBER 1995
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
serial-control interface
This device uses the least-significant-bit-first format. Therefore, for a 16-bit word, D15 is the most significant
bit and D0 is the least significant bit. Unless otherwise specified, all values are in 2s-complement format.
serial-control-data input
The 16-bit control-data input implements the device-control functions. The TMS57014A has two registers for
this data: the system register and the attenuation register. The system register contains most of the system
configuration information, and the attenuation register controls audio output level, de-emphasis, and mute.
Figure 3 illustrates the input timing for ATT, SHIFT, and LATCH. The data loads internally on the falling edge
of LATCH. The shift clock should be high for the LATCH setup time before LATCH goes low.
01
234
5
6
7
8
9
10
11
12
13
14
15
MSB
LSB
SHIFT
ATT
LATCH
Figure 3. Control-Data-Input Timing
mute
When mute is activated, the output PWM becomes zero data (50% duty cycle). The two mute flags, MUTEL
and MUTER, are independently set low based on the data in the respective channel being zero. This function
becomes active under the following conditions:
1.
When the zero-data detector detects that the input data has been zero for 2500 cycles of Fs or 12500
cycles of Fs (as selected in the control registers), output is 50% duty cycle.
2.
When the MUTE register value is set high by means of the serial-control data.
3.
When INIT is active (low), output is 50% duty cycle.
zero-data detect
After the input data remains zero for 2500 or 12 500 cycles of Fs as set by the system register (D4, D5), the
channel-mute flag becomes active. Zero-data detection is available for both channels independently, so the two
outputs (MUTER and MUTEL) indicate that zero data has been detected on the respective channel. The
zero-detect register value in the serial-control data selects the detection period. The mute flag returns high
immediately when nonzero input data is received.
de-emphasis filter
Four sets of de-emphasis-filter coefficients support four sampling rates (Fs): 32, 37.8, 44.1, and 48 kHz. Internal
register values select the filter coefficients. The internal register values enable or disable the filter. Figure 4
illustrates the de-emphasis characteristics.
Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the
de-emphasis characteristics shown in Figure 4. This device provides reconstruction of the original frequency
response.
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