
1
Features
TMS320C6474
Multicore Digital Signal Processor
www.ti.com
SPRS552 – OCTOBER 2008
High-Performance Multicore DSP (C6474)
Antenna Interface
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1-ns Instruction Cycle Time
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6 Configurable Links (Full Duplex)
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1.0-GHz Clock Rate
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Supports OBSAI RP3 Protocol, v1.0
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Eight 32-Bit Instructions/Cycle
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768-Mbps, 1.536-, 3.072-Gbps Link Rates
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Commercial Temperature 0
°C to 100°C
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Supports CPRI Protocol V2.0
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614.4-Mbps, 1.2288-, 2.4576-Gbps Link
3 TMS320C64x+ DSP Cores
Rates
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Dedicated SPLOOP Instructions
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Clock Input Independent or Shared with
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Compact Instructions (16-Bit)
CPU (Selectable at Boot-Time)
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Exception Handling
Two 1x Serial RapidIO Links, v1.2 Compliant
TMS320C64x+ Megamodule L1/L2 Memory
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1.25-, 2.5-, 3.125-Gbps Link Rates
Architecture
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Message Passing and DirectIO Support
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256 K-Bit (32 K-Byte) L1P Program Cache
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Error Management Extensions and
[Direct Mapped]
Congestion Control
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256 K-Bit (32 K-Byte) L1D Data Cache
One 1.8-V Inter-Integrated Circuit (I2C) Bus
[2-Way Set-Associative]
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24 M-Bit (3072 K-Byte) Total L2 Unified
Two 1.8-V McBSPs
Mapped RAM/Cache [Flexible Allocation]
1000 Mbps Ethernet MAC (EMAC)
Configurable at boot-time to 1 MB/
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IEEE 802.3 Compliant
1 MB/1 MB or 1.5 MB/1 MB/0.5 MB
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Supports SGMII, v1.8 Compliant
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512 K-Bit (64 K-Byte) L3 ROM
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8 Independent Transmit (TX) and 8
Enhanced VCP2
Independent Receive (RX) Channels
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Supports Over 694 7.95-Kbps AMR
Six 64-Bit General-Purpose Timers
Enhanced Turbo Decoder Coprocessor (TCP2)
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Configurable up to Twelve 32-Bit Timers
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Supports up to Eight 2-Mbps 3 GPP
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Configurable in a Watchdog Timer mode
(6 Iterations)
16 General-Purpose I/O (GPIO) Pins
Endianness: Little Endian, Big Endian
Internal Semaphore Module
Frame Synchronization Interface
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Software Method to Control Access to
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Time Alignment Between Internal
Shared Resources
Subsystems, External Devices/System
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32 General Purpose Semaphore Resources
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OBSAI RP1 Compliant for Frame Burst Data
System PLL and PLL Controller
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Alternate Interfaces for non-RP1 and
DDR PLL and PLL Controller, Dedicated to
non-UMTS Systems
DDR2 Memory Controller
16-/32-Bit DDR2-667 Memory Controller
Supports IP Security
EDMA3 Controller (64 Independent Channels)
IEEE-1149.1 and IEEE-1149.6 (JTAG)
Boundary-Scan-Compatible
561-Pin Ball Grid Array (BGA) Packages (CUN,
GUN, or ZUN Suffix), 0.8-mm Ball Pitch
0.065-m/7-Level Cu Metal Process (CMOS)
SmartReflex Class 0 Enabled - 0.9-V to 1.2-V
Adaptive Core Voltage
1.8-V, 1.1-V I/Os
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
TMS320C64x+, SmartReflex, TMS320C6000, VelociTI, C64x+, C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas
Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.