Electrical Specifications
117
June 2004
SPRS257
6.24
External Interface Write Timing
Table 6
28. External Memory Interface Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
d(XWEL-XD)
t
h(XA)XZCSH
t
h(XD)XWE
t
dis(XD)XRNW
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = Trail period, write access. See Table 6
24.
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
1
3
2
2
2
1
ns
ns
ns
ns
ns
ns
2
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
2
0
1
ns
ns
Delay time, data valid after XWE active low
4
ns
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
ns
ns
ns
TW
2
4
Lead
Active
Trail
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOHL-XZCSH)
t
en(XD)XWEL
t
h(XD)XWEH
t
dis(XD)XRNW
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment
cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
DOUT
XREADY
t
d(XWEL-XD)
Figure 6
27. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
N/A
N/A = “Don’t care” for this example
XRDACTIVE
N/A
XRDTRAIL
N/A
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A
0
0
≥
1
≥
0
≥
0
A