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参数资料
型号： TMX320R2812ZHHQ
厂商： Texas Instruments, Inc.
元件分类： 数字信号处理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812数字信号处理器
文件页数： 121/147页
文件大小： 2021K
代理商： TMX320R2812ZHHQ
Electrical Specifications
121
June 2004
SPRS257
6.26
External Interface Ready-on-Write Timing With One External Wait State
Table 6
33. External Memory Interface Write Switching Characteristics
(Ready-on-Write, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XWEL)
t
d(XCOHL-XWEH)
t
d(XCOH-XRNWL)
t
d(XCOHL-XRNWH)
t
en(XD)XWEL
t
d(XWEL-XD)
t
h(XA)XZCSH
t
h(XD)XWE
t
dis(XD)XRNW
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
TW = trail period, write access (see Table 6
24)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/W low
1
3
2
2
2
1
ns
ns
ns
ns
ns
ns
2
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE low
2
0
1
ns
ns
Delay time, data valid after XWE active low
4
ns
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE inactive high
Data bus disabled after XR/W inactive high
ns
ns
ns
TW
2
4
Table 6
34. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
§
MIN
MAX
UNIT
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
e(XRDYsynchH)
t
su(XRDYsynchH)XCOHL
t
h(XRDYsynchH)XZCSH
§
The first XREADY (Synch) sample occurs with respect to E in Figure 6
30:
E =(XWRLEAD + XWRACTIVE) t
c(XTIM)
When first sampled, if XREADY (Synch) is found to be high, then the access will complete. If XREADY (Synch) is found to be low, it will be sampled
again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D =(XWRLEAD + XWRACTIVE +n
1) t
c(XTIM)
t
su(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Synch) low before XCLKOUT high/low
Hold time, XREADY (Synch) low
Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Synch) high before XCLKOUT high/low
Hold time, XREADY (Synch) held high after zone chip select high
15
12
ns
ns
ns
ns
ns
3
15
0
Table 6
35. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
MIN
MAX
UNIT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
t
h(XRDYasynchH)XZCSH
The first XREADY (Synch) sample occurs with respect to E in Figure 6
31:
E = (XWRLEAD + XWRACTIVE
2) t
c(XTIM)
When first sampled, if XREADY (Asynch) is found to be high, then the access will complete. If XREADY (Asynch) is found to be low, it will be
sampled again each t
c(XTIM)
until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE
3 + n) t
c(XTIM)
t
su(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Setup time, XREADY (Asynch) low before XCLKOUT high/low
Hold time, XREADY (Asynch) low
Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge
Setup time, XREADY (Asynch) high before XCLKOUT high/low
Hold time, XREADY (Asynch) held high after zone chip select high
11
8
ns
ns
ns
ns
ns
3
11
0
A
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