参数资料
型号: TPA3005D2PHPR
厂商: Texas Instruments
文件页数: 10/31页
文件大小: 0K
描述: IC AMP AUDIO PWR 6W STER 48TQFP
标准包装: 1
类型: D 类
输出类型: 2 通道(立体声)
在某负载时最大输出功率 x 通道数量: 6W x 2 @ 8 欧姆
电源电压: 8.5 V ~ 18 V
特点: 差分输入,短路保护和热保护,关机
安装类型: 表面贴装
供应商设备封装: 48-HTQFP(7x7)
封装/外壳: 48-TQFP 裸露焊盘
包装: 标准包装
产品目录页面: 877 (CN2011-ZH PDF)
配用: 296-18924-ND - EVAL MODULE FOR TPA3005D2
其它名称: 296-17058-6
SLOS427A – MAY 2004 – REVISED AUGUST 2010
www.ti.com
Decoupling capacitors—The high-frequency 0.1-F decoupling capacitors should be placed as close to the
PVCC (pins 14, 15, 22, 23, 38, 39, 46, and 47) and AVCC (pin 33) terminals as possible. The V2P5 (pin 4)
capacitor, AVDD (pin 29) capacitor, and VCLAMP (pins 25, 36) capacitor should also be placed as close to the
device as possible. Large (10 F or greater) bulk power supply decoupling capacitors should be placed near
the TPA3005D2 on the PVCCL, PVCCR, and AVCC terminals.
Grounding—The AVCC (pin 33) decoupling capacitor, AVDD (pin 29) capacitor, V2P5 (pin 4) capacitor, COSC
(pin 28) capacitor, and ROSC (pin 27) resistor should each be grounded to analog ground (AGND, pin 26 and
pin 30). The PVCC decoupling capacitors should each be grounded to power ground (PGND, pins 18, 19, 42,
and 43). Analog ground and power ground may be connected at the PowerPAD, which should be used as a
central ground connection or star ground for the TPA3005D2. Basically, an island should be created with a
single connection to PGND at the PowerPAD.
Output filter—The ferrite EMI filter (Figure 19) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 18) should be placed close to the outputs. The capacitors
used in both the ferrite and LC filters should be grounded to power ground. If both filters are used, the LC
filter should be placed first, following the outputs.
PowerPAD—The PowerPAD must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the PowerPAD thermal land should be 5 mm by 5 mm (197 mils by 197 mils).
The PowerPAD size measures 4,55 x 4,55 mm. Four rows of solid vias (four vias per row, 0,3302 mm or 13
mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid
copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not
thermal relief or webbed vias. For additional information, see the PowerPAD Thermally Enhanced Package
application note, (SLMA002).
For an example layout, see the TPA3005D2 Evaluation Module (TPA3005D2EVM) User Manual, (SLOU165).
Both the EVM user manual and the PowerPAD application note are available on the TI Web site at
http://www.ti.com.
18
Copyright 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPA3005D2
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