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参数资料
| 型号： | TPS2501DRCT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 1075 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封装： | 3 X 3 MM, 0.90 MM HEIGHT, PLASTIC, SON-10 |
| 文件页数： | 4/41页 |
| 文件大小： | 1641K |
| 代理商： | TPS2501DRCT |
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SLVS886C – OCTOBER 2008 – REVISED AUGUST 2010
www.ti.com
The USB switch is powered directly from VAUX and turns on once the UVLO of the USB switch is met (4.3 V
typical). The turnon is controlled internally to provide a monotonic start-up on VUSB.
Normal Operation
The boost converter runs at a 1-MHz fixed frequency and regulates the output voltage VAUX using a pulse-width
modulating (PWM) topology that adjusts the duty cycle of the low-side N-channel MOSFET on a cycle-by-cycle
basis. The PWM latch is set at the beginning of each clock cycle and commands the gate driver to turn on the
low-side MOSFET. The low-side MOSFET remains on until the PWM latch is reset.
Voltage regulation is controlled by a peak-current-mode control architecture. The voltage loop senses the voltage
on VAUX and provides negative feedback into an internal, transconductance-error amplifier with internal
compensation and resistor divider. The output of the transconductance-error amplifier is summed with the output
of the slope-compensation block and provides the error signal that is fed into the inverting input of the PWM
comparator. Slope compensation is necessary to prevent subharmonic oscillations that may occur in
peak-current-mode control architectures that exceed 50% duty cycle. The PWM ramp fed into the noninverting
input of the PWM comparator is provided by sensing the inductor current through the low-side N-channel
MOSFET. The PWM latch is reset when the PWM ramp intersects the error signal and terminates the pulse
width for that clock period. The TPS2500 stops switching if the peak-demanded current signal from the error
amplifier falls below the zero-duty-cycle threshold of the device.
Low-Frequency Mode
The TPS2500 enters low-frequency mode above VIN = VLFM (4.35 V typical) by reducing the dc/dc converter
frequency from 1 MHz (typical) to 250 kHz (typical). Current-mode control topologies require internal
leading-edge blanking of the current-sense signal to prevent nuisance trips of the PWM control MOSFET. The
consequence of leading-edge blanking is that the PWM controller has a minimum controllable on-time (85 ns
typical) that results in a minimum controllable duty cycle. In a boost converter, the demanded duty cycle
decreases as the input voltage increases. The boost converter pulse-skips if the demanded duty cycle is less
than what the minimum controllable on-time allows, which is undesirable due to the excessive increase in
switching ripple. When the TPS2500 enters low-frequency mode above VIN = VLFM, the minimum controllable
duty cycle is increased because the minimum controllable on-time is a smaller percentage of the entire switching
period. Low-frequency mode prevents pulse skipping at voltages larger than VLFM. The TPS2500 resumes normal
1-MHz switching operation when VIN decreases below VLFM.
One effect of reducing the switching frequency is that the ripple current in the inductor and output AUX
capacitors is increased. It is important to verify that the peak inductor current does not exceed the peak switch
current limit ISW (4.5 A typical) and that the increase in AUX ripple is acceptable during low-frequency mode.
No-Frequency Mode
The TPS2500 enters no-frequency mode above VIN = VNFM (5.05 V typical) by disabling the oscillator and turning
on the high-side synchronous PMOS 100% of the time. The input voltage is now directly connected to the AUX
output through the inductor and high-side PMOS. Power dissipation in the device is reduced in no-frequency
mode because there is no longer any switching loss and no RMS current flows through the low-side control
NMOS, which results in higher system-level efficiency. The boost converter resumes switching when VIN falls
below VNFM.
Eco-mode Light-Load Operation
The TPS2500 enters the Eco-mode control scheme at light loads to increase efficiency. The device reduces
power dissipation while in the Eco-mode control scheme by disabling the gate drivers and power MOSFETs and
entering a pulsed-frequency mode (PFM). PFM works by disabling the gate driver when the PFM latch is set.
During this time period there is no switching, and the load current is provided solely by the output capacitor.
There are two comparators that determine when the device enters or leaves the Eco-mode control scheme. The
first comparator is the PFM-enter comparator. The PFM-enter comparator monitors the peak demanded current
in the inductor and allows the device to enter the Eco-mode control scheme when the inductor current falls below
IINDLOW (420 mA typical). The second comparator is the AUX-low comparator. The AUX-low comparator
monitors AUX and forces the converter out of the Eco-mode control scheme and resumes normal operation
when the voltage on AUX falls below AUXLOW (5 V typical). The Eco-mode control scheme is disabled during
low-frequency mode when VIN > VLFM (4.35 V typical).
12
Copyright 2008–2010, Texas Instruments Incorporated
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