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参数资料
| 型号： | TPS3619-33DGKR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封装： | 3.05 X 4.98 MM, GREEN, PLASTIC, MSOP-8 |
| 文件页数： | 11/17页 |
| 文件大小： | 494K |
| 代理商： | TPS3619-33DGKR |
www.ti.com
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
SLVS387H – APRIL 2001 – REVISED DECEMBER 2007
At specified temperature range.
MIN
MAX
UNIT
Supply voltage, VDD
1.65
5.5
V
Battery supply voltage, VBAT
1.5
5.5
V
Input voltage, VI
0
VDD + 0.3
V
High-level input voltage, VIH
0.7 x VDD
V
Low-level input voltage, VIL
0.3 x VDD
V
Continuous output current at VOUT, IO
300
mA
Input transition rise and fall rate at MR
100
ns/V
Slew rate at VDD or VBAT, Δ t/ΔV
1
V/
s
Operating free-air temperature range, TA
–40
+85
°C
Over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 1.8 V,
IOH = –400 A
VDD – 0.2 V
RESET
VDD = 3.3 V,
IOH = –2 mA
VDD – 0.4 V
V
VDD = 5 V,
IOH = –3 mA
VDD – 0.4 V
VOH
High-level output voltage
VDD = 1.8 V,
IOH = –20 A
VDD – 0.3 V
PFO
VDD = 3.3 V,
IOH = –80 A
VDD – 0.4 V
V
VDD = 5 V,
IOH = –120 A
VDD – 0.4 V
VDD = 1.8 V,
IOL = –400 A
0.2
VOL
Low-level output voltage
RESET PFO
VDD = 3.3 V,
IOL = 2 mA
0.4
V
VDD = 5 V,
IOL = 3 mA
0.4
IOL = 20 A, VBAT > 1.1 V or
Vres
Power-up reset voltage (see (1))
0.4
V
VDD > 1.1 V
IOUT = 8.5 mA,
VDD = 1.8 V
VDD – 50 mV
VBAT = 0 V
IOUT = 125 mA,
Normal mode
VDD = 3.3 V
VDD – 150 mV
V
VBAT = 0 V
IOUT = 200 mA,
VOUT
VDD = 5 V
VDD – 200 mV
VBAT = 0 V
IOUT = 0.5 mA,
VDD = 0 V
VBAT – 20 mV
VBAT = 1.5 V
Battery-backup mode
V
IOUT = 7.5 mA,
VBAT – 113 mV
VBAT = 3.3 V
VDD to VOUT on-resistance
VDD = 5 V
0.6
1
rDS(on)
VBAT to VOUT on-resistance
VDD = 3.3 V
8
15
TPS3619-33
2.88
2.93
3
VIT–
Negative-going input
TPS3619-50
TA = –40°C to 85°C
4.46
4.55
4.64
V
threshold voltage (see (2))
VPFI
PFI
1.13
1.15
1.17
1.65 V < VIT < 2.5 V
20
VIT
2.5 V < VIT < 3.5 V
40
3.5 V < VIT < 5.5 V
60
Vhys
Hysteresis
mV
PFI
12
VBSW
VDD = 1.8 V
55
(see (3))
(1)
The lowest supply voltage at which RESET becomes active. tr,VDD ≥ 15 s/V.
(2)
To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1
F) should be placed near the supply terminals.
(3)
For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT.
Copyright 2001–2007, Texas Instruments Incorporated
3
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