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| 型号： | TPS40130RHBR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封装： | GREEN, PLASTIC, QFN-32 |
| 文件页数： | 24/38页 |
| 文件大小： | 950K |
| 代理商： | TPS40130RHBR |
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Differential Amplifier Signals
High-Current Connections and Routing
Device Decoupling for VIN5 and BP5
Symmetry
SW Node
Lower MOSFET Gate Drive, LDRV1 and LDRV2
Upper MOSFET Gate Drive, HDRV1 and HDRV2
SLUS602B – JUNE 2004 – REVISED SEPTEMBER 2005
LAYOUT CONSIDERATIONS (continued)
Routing
The traces that connect to C5 and C4 should be made directly at the capacitor(s) and routed on an internal
signal plane to CS1, CSRT1 and CS2, CSRT2, respectively. In addition, a small value of R-C filter may be used
on the CSx and CSRTx lines, with these components placed close to the device. A 5.1-
resistor in series with
the CSx and CSRTx lines and a 100-pF capacitor between the CSx and CSRTx lines, provides additional
filtering, a prudent measure since the level of switching noise in a given layout is not fully known until the board
is being tested for the first time.
The differential amplifier provides optimum regulation at the load point.
Connection
The signal connections for VOUT and GSNS should be made across the closest capacitor to the load point. This
ensures the most accurate DC sensing and most noise free connection also.
Routing
Since the load point may be physically several inches, or more, from the device, it is very likely that the VOUT
and GSNS inputs to the differential amplifier are corrupted by switching noise. The signals should be routed on
an internal layer, and the R-C filter approach recommended for the CSx and CSRTx lines is applicable for these
lines as well.
The 1.0-F decoupling capacitor for VIN5 should be placed close to pins 1 and 30 of the device. The decoupling
capacitor for BP5 should be placed close to pins 22 and 23 of the device.
Symmetry is especially important in the power processing components when considering the device placement
between the two phases. Input ceramic decoupling capacitors should be placed close to the upper MOSFETs
and the current path from the upper MOSFET drain to the lower MOSFET source should be on the PGND with
maximum copper area. Output capacitors should be placed symmetrically between the output inductor and lower
MOSFET for each phase.
The SW node consists of the source of the upper MOSFET, the drain of the lower MOSFET,and the output
inductor. These components should be placed to minimize the area of the SW node. The area of the SW node
determines the amount of stray capacitance and inductance that causes ringing during switching transitions.
A resistor, with a value of between approximately 1.0
and 2.2 should be placed between LDRVx and the
gate of the respective MOSFET. The resistors are necessary if the falling SW node pulls the gate voltage below
GND. This can occur if the MOSFET QGD is larger than QGS. The traces for LDRVx should be wide, (0.05 to 0.1
inches) and routed on the top layer if possible. If routing must go to another layer, use multiple vias for
interconnect. The return signal from the MOSFET drain to PGND on the device should be as wide as the return
for LDRVx.
The traces for HDRVx and SWx should be wide, (0.05 to 0.1inches), and routed on the top layer if possible. If
routing must go to another layer, use multiple vias for interconnect.
30
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