参数资料
型号: TPS40195PWG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 580 kHz SWITCHING FREQ-MAX, PDSO16
封装: GREEN, PLASTIC, TSSOP-16
文件页数: 18/43页
文件大小: 1086K
代理商: TPS40195PWG4
Component Selection for the TPS40195
(
)
(
)
f
7
T
S
2.5
10
2.5
10
R
83.3k
300
=
W
(25)
(
)
ON
OFF
UVLO1
6
UVLO
V
7
6
R
192.3k
I
5.2
10
-
=
W
(26)
(
)
UVLO
UVLO2
UVLO1
ON
UVLO
V
1.26
R
192.3k
42.2k
7 1.26
V
=
=
W
=
W
-
(27)
START
OUT
t
2
L
C
p
(28)
( )
6
START
t
6.28
2.5
10
300
10
0.172ms
-
=
(29)
f
DAC
SS
SW
N
1024
t
0.591
2.0 ms
300
=
=
=
(30)
www.ti.com ........................................................................................................................................ SLUS720D – FEBRUARY 2007 – REVISED NOVEMBER 2008
Estimating the body diode losses based on a forward voltage of 1.0 V yields 0.162 W. The gate losses are
unknown at this time so assume 0.1 W gate losses. This leaves 0.338 W for conduction losses. Using this figure
a target RDS(on) of 4.0 m was calculated. The SI7886ADP has an RDS(on) maximum of 4.8 m and was used for
this design.
Using the parameters from its data sheet the actual expected power losses were calculated. Conduction loss is
0.394 W, body diode loss is 0.210 W and the gate loss was 0.063 W. This totals 0.667 W associated with the
rectifier MOSFET.
The ratio between Cgs and Cgd should be greater than one. The Si7886 capacitor meets this criterion and helps
reduce the risk of dv/dt induced turn on of the rectifier MOSFET. If this is likely to be a problem a small resistor
may be added in series with the boost capacitor, CBOOST. to slow the turn on speed of QSW at the expense of
increased switching losses in that device.
Timing Resistor, RT
The timing resistor is calculated using the following equation.
A standard value resistor of 82.5 k
is used.
Setting UVLO
The equations below are used to set the UVLO voltages.
The UVLO threshold voltage ( VUVLO) is 1.26 V. The module has a turn on voltage of 7 V and a turn off voltage of
6 V. This sets RUVLO1to 191 k, the nearest standard value. The second resistor RUVLO2 is 42.2 k.
Setting the Soft-Start Time
The selection of the soft start time should be greater than the time constant of the output filter, LOUT and COUT.
This time is given in Equation 28 and Equation 29.
The soft-start time is determined using Equation 30 . The TPS40195 uses a counter operating at the clock
frequency that increments an internal DAC until it reaches the turn on threshold voltage of 0.591 V. The number
of counts required to reach this threshold is determined by one of three settings on the SS pin. In this case, the
pin is floating (with a small bypass capacitor) which sets the clock count (NDAC) to 1024 and the soft-start time is
2.0 ms
Copyright 2007–2008, Texas Instruments Incorporated
25
Product Folder Link(s): TPS40195
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