参数资料
型号: TPS40197RGYR
厂商: TEXAS INSTRUMENTS INC
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 520 kHz SWITCHING FREQ-MAX, PQCC16
封装: PLASTIC, MO-241BB, VQFN-16
文件页数: 9/30页
文件大小: 931K
代理商: TPS40197RGYR
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G
SW
G high
G low
I
f
Q
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TI Information — Selective Disclosure
www.ti.com
SLUS886 – NOVEMBER 2008
For regulator stability, a 1-mF capacitor is required to be connected from BP to GND. In some applications using
higher gate charge MOSFETs, a larger capacitor is required for noise suppression. For a total gate charge of
both the high-side and low-side MOSFETs greater than 20 nC, a 2.2-mF or larger capacitor is recommended.
where
IG is the required gate drive current
fSW is the switching frequency
QG(high) is the gate charge requirement for the high-side FET when VGS = 5 V
QG(low) is the gate charge requirement for the low-side FET when VGS = 5 V
(6)
Pre-Bias Startup
The TPS40197 contains a unique circuit to prevent current from being pulled from the output during startup in the
condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level
(internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous
rectification by starting the first LDRV pulse with a narrow on-time. It then increments that on-time on a
cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter.
This scheme prevents the initial sinking of the pre-bias output, and ensures that the output voltage (VOUT) starts
and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased startup to
normal mode operation with minimal disturbance to the output voltage. The amount of time from the start of
switching until the low-side MOSFET is turned on for the full (1-D) interval is defined by 32 clock cycles.
Drivers
The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate-to-source voltage of 5 V.
The LDRV driver switches between BP and GND, while HDRV driver is referenced to SW and switches between
BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit to
minimize body diode conduction in the synchronous rectifier. The drivers are capable of driving MOSFETS that
are appropriate for a 15-A converter.
Power Good
The TPS40197 provides an indication that output power is good for the converter. This is an open drain signal
and pulls low when any condition exists that would indicate that the output of the supply might be out of
regulation. These conditions include:
VFB is more than 10% from the reference voltage based on VID codes
soft-start is active
an undervoltage condition exists for the device
a short-circuit condition has been detected
die temperature is over (140°C)
NOTE
When there is no power to the device, PGOOD is not able to pull close to GND if an
auxiliary supply is used for the power good indication. In this case, a built in resistor
connected from drain to gate on the PGOOD pull down device makes the PGOOD pin
look approximately like a diode to GND.
Thermal Shutdown
If the junction temperature of the device reaches the thermal shutdown limit of 140°C, the PWM and the oscillator
are turned off and HDRV and LDRV are driven low, turning off both FETs. When the junction cools to the
required level (120°C nominal), the PWM initiates soft-start as during a normal power-up cycle.
Copyright 2008, Texas Instruments Incorporated
17
Product Folder Link(s): TPS40197
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