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参数资料
| 型号： | TPS43000PWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | GREEN, TSSOP-16 |
| 文件页数： | 3/31页 |
| 文件大小： | 615K |
| 代理商： | TPS43000PWRG4 |
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TPS43000
SLUS489 OCTOBER 2001
11
www.ti.com
APPLICATION INFORMATION
When the RDS(on) of the MOSFET is used as the sense element, several issues arise. Before the IZERO
comparator is enabled, the MOSFET must be fully enhanced, and the drain-to-source voltage must be allowed
to settle. The TPS43000 has an internal circuit that enables the IZERO comparator approximately 40 ns after
the rectifier MOSFET is enhanced.
NOTE: For the SEPIC topology, the voltage on the drain of the rectifier MOSFET swings to VIN
when the energizing MOSFET is on. Therefore, in order to prevent the SWP input pin from being
damaged, it must connect to a Schottky diode clamp to ground.
PFM mode
For improved efficiency at light loads, the TPS43000 can be programmed to automatically enter PFM (Pulse
Frequency Modulation) mode by connecting the PFM pin to ground. PFM is initiated by the IZERO comparator
used for synchronous rectifier commutation. An internal digital counter is used to count the number of IZERO
pulses at the output of the IZERO comparator. When seven IZERO pulses occur, the controller enters sleep state
until the voltage at the FB pin falls to approximately 784 mV (output voltage drops 2% below nominal). At this
time, the controller turns back on and operates at its fixed-frequency for a short duration (load dependent,
typically 10 to 200 PWM cycles) increasing the output voltage. The cycle repeats when another seven IZERO
pulses occur. This results in a very low duty cycle of operation, reducing all losses and improving light load
efficiency. During the sleep state, most of the circuitry internal to the TPS43000 is powered down. This reduces
quiescent current, which lowers the average dc operating current, enhancing its efficiency. The error amplifier
output is disconnected from the COMP pin during the sleep state. The COMP pin goes to high impedance and
maintains approximately the same voltage level it was at when it entered the sleep state. This minimizes error
amplifier overshoot/undershoot when coming out of the sleep state. The user can disable PFM by connecting
the PFM pin to VIN.
low power mode
At relatively high gate drive voltages, gate drive losses can become excessive and begin to dominate under light
load conditions. The expression for gate drive power loss is given by equation (2). The power varies as a function
of the applied gate voltage squared.
P
GATELOSS +
Q
G
V
G
2
f
V
S
,
where QG is the total gate charge, VS is the gate voltage specified in the MOSFET manufacturer’s data sheet,
VG is the applied gate drive voltage, and f is the switching frequency.
When both VIN and VOUT are above 3.6 V, the TPS43000 automatically enters LP mode and selects the lower
voltage of VIN or VOUT to provide the gate drive voltage on the NDRV pin. This minimizes gate drive losses
at relatively high input and output voltages and helps maintain high efficiency at light loads. The PDRV pin
remains powered by either VIN (buck topology) or VOUT (boost, flyback, and SEPIC topologies) via the VP
power input pin.
To help provide a smooth transition in and out of LP mode, its circuitry has 300 mV of hysteresis. When either
VIN or VOUT drops below 3.3 V, the TPS43000 transitions back to normal mode and the NDRV pin is powered
by the higher potential of VIN or VOUT.
(2)
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