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参数资料
| 型号： | TPS43000PWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | GREEN, TSSOP-16 |
| 文件页数： | 8/31页 |
| 文件大小： | 615K |
| 代理商： | TPS43000PWRG4 |
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TPS43000
SLUS489 OCTOBER 2001
16
www.ti.com
APPLICATION INFORMATION
With voltage-mode control, the closed-loop design goal for each of the topologies with the Type III error amplifier
compensation is to set the crossover frequency above the resonant frequency of the LC filter (prevents filter
oscillations during a transient response), but below the lowest possible RHP zero frequency. This is
accomplished by setting the two zeros in the compensation network before the LC double pole frequency. This
provides a phase boost. The two poles should be placed a decade above the crossover frequency.
The following is a typical procedure for selecting the loop compensation values for a buck converter operated
in CCM:
Step 1. Select the desired crossover frequency a decade above the LC pole frequency.
Step 2. Set the resistor divider formed by R1 and RBIAS to develop the desired regulation voltage. Note that
RBIAS sets the dc operating point of the loop, but has no effect on ac operation and does not factor into
the loop compensation calculations.
Step 3. Set the zero formed by R1 and C3 to approximately one-half decade above the LC double pole to
compensate for the phase loss.
Step 4. Set the zero formed by R2 and C1 to approximately one-half decade below the LC double pole to avoid
a conditional instability.
Step 5. Set the pole formed by R3 and C3 to cancel the ESR zero of the output capacitor.
Step 6. Set the pole formed by R2 and C2 to approximately one-half decade above the crossover frequency.
If the converter is operated in DCM, the lead network (R3 and C3 in Figure 2) can be eliminated for all topologies.
This configuration is referred to as a Type II error amplifier compensation network and has a pole at the origin
and a single zero-pole pair. It can provide up to 90
° of phase boost. The frequency of the pole and zero are
defined by the following equations:
zero
f
z1 +
1
(2
p
R2
C1)
pole
f
p1 [
1
(2
p
R2
C2)
, Assuming C1
C2
The zero-pole pair is used to compensate for the power circuit’s ESR zero and the pole formed by the output
capacitor and the effective output resistance.
(15)
(16)
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