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参数资料
| 型号： | TPS51020DBTRG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 7/28页 |
| 文件大小： | 0K |
| 描述： | IC DUAL DC/DC SYNC CTRLR 30TSSOP |
| 标准包装： | 2,000 |
| 应用： | 控制器，DDR，DDR2 |
| 输入电压： | 4.5 V ~ 28 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 24 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 30-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 30-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | 296-18958-ND - EVAL MODULE FOR TPS51020-001 296-17268-ND - EVALUATION MODULE FOR TPS51100 296-12357-ND - EVAL MOD FOR TPS2330-185 |
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TPS51020
SLUS564C ? JULY 2003 ? REVISED OCTOBER 2008
ENBL1
ENBL1
470
ENBL2
5.0
3.6
fSW ? Switching Frequency ? kHz
27 0 36 0
4 70
36 0
SSTRT1
27 0
C
ENBL2
5.0
3.6
fSW ? Switching Frequency ? kHz
36 0 36 0
27 0 27 0
SSTRT1
27 0
1.5
1.2
0
B
A
1.5
1.2
0
5.0
3.6
SSTRT2
C
5.0
3.6
SSTRT2
B
1.5
1.2
0
t0 t1
t2
t3
t4
t5
A
1.5
1.2
0
t0 t1
t2
t3
t4
t5
t ? Time
RSSTRT1 = RSSTRT2 = OPEN = 450 kHz
Figure 1
TERMINAL FUNCTIONS
TERMINAL
t ? Time
RSSTRT1 = 1 M ? , RSSTRT2 = OPEN = 360 kHz
Figure 2
NAME
COMP1
COMP2
NO.
2
14
I/O
O
O
DESCRIPTION
Error amplifier output. Connect feedback network to this pin and INVx for compensation of control loop.
DDR selection pin. If this pin is grounded, the device runs in DDR Mode. The error amplifier reference for VO2
is (VO1_VDDQ)/2, the REF_X output voltage becomes (VO1_VDDQ)/2 and skip mode is disabled for VO2,
DDR
6
I
Also, VREG5 is turned off when both ENBLx are at low in this mode. If this pin is at 2.2-V or higher, the device
runs in ordinary dual SMPS mode (dual mode), then the error amplifier reference for VO2 is connected to inter-
nal 0.85-V reference, the REF_X output voltage becomes 10 V, V REG5 is kept on regardless of ENBLx status.
CAUTION: Do not toggle DDR while ENBL1 or ENBL2 are high. (See Table 2)
ENBL1
9
I
TTL Enable Input. If ENBLx is greater than 2.2 V, then the VREG5 is enabled (DDR mode) and the SMPS of
that channel attempts to turn on. If both ENBL1 and ENBL2 are low then the 10-V (or (VO1_VDDQ) /2 output)
ENBL2
GND
INV1
INV2
LL1
LL2
OUT1_D
OUT2_D
OUT1_U
OUT2_U
OUTGND1
OUTGND2
10
7
1
15
28
18
27
19
29
17
26
20
I
O
I
I
I/O
I/O
O
O
O
O
O
O
voltage as well as the oscillator are turned off. (See Table 2)
Signal ground pin.
Error amplifier inverting input. Also input for skip comparator, and OVP/UVP comparators.
Switch-node connection for high-side driver and overcurrent protection circuitry.
Synchronous N-channel MOSFET driver outp ut.
High-side N-channel MOSFET driver outp ut.
Ground return for OUTx_D.
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