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参数资料
| 型号： | TPS51020DBTRG4 |
| 厂商： | Texas Instruments |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC DUAL DC/DC SYNC CTRLR 30TSSOP |
| 标准包装： | 2,000 |
| 应用： | 控制器，DDR，DDR2 |
| 输入电压： | 4.5 V ~ 28 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 24 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 30-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 30-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | 296-18958-ND - EVAL MODULE FOR TPS51020-001 296-17268-ND - EVALUATION MODULE FOR TPS51100 296-12357-ND - EVAL MOD FOR TPS2330-185 |
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TPS51020
SLUS564C ? JULY 2003 ? REVISED OCTOBER 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
PGOOD
NO.
12
I/O
O
DESCRIPTION
Power good output. This is an open drain pull-down pin for power good. It remains l ow during soft-start until
both outputs become within ± 7.5%. If INV1 or INV2 is out of regulation, or VREG5V goes under UVLO then this
pin goes low. The internal delay timer counts 2048 clks at low to high (by design, no delay for hi gh to low ). If
ENBLx is low, and the power good output is high, then the power good signal for that channel is ignored.
10-V N-channel MOSFET bias or (VO1_VDDQ)/2 reference output. If dual mode is selected (DDR > 2.2 V)
REF_X
8
O
then this pin provides a low 10-V current (< 2 mA) bias, dropped down from VIN, for the SO – S5 switched
N-channel MOSFETs. If DDR mode is selected (DDR = GND) then this pin becomes (VO1_VDDQ)/2 capable
of 3 mA source current. This bias/reference is shut off when ENBL1 and ENBL2 are both low. (See Table 2)
REG5_IN
SSTRT1
SSTRT2
21
3
13
I
I
I
External 5V regulator Input. If this pin is above 4.7 V, then the 5 V circuit bias switches from the VREF5 to the
supply presented to REG5_IN.
Soft-start/frequency select input. Connect a capacitor between SSTRTx and ground for adjusting the softstart
time. A constant current fed to this capacitor ramps the reference during startup . Frequency selection is de-
scribed in Table 1. The soft-start capacitor is discharged upon UVLO/OVP/UVP, or when ENBLx is asserted
low.
Skip mode selection pin. Ground for automatic control between PWM mode in heavy load and hysteretic op-
SKIP
4
I
eration in light load. Tie high for PWM only operation for the entire load condition. If DDR is grounded, then skip
mode is disabled for Channel 2.
Channel 1 overcurrent trip point voltage input. Connect a resistor between TRIP1 and the high-side N-channel
TRIP1
25
I
MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down. Connect
resistor between TRIP1 and GND for low-side N-channel MOSFET overcurrent latch shutdown.
Channel 2 overcurrent trip point voltage input. Connect a resistor between TRIP2 and the high-side N-channel
MOSFET input conversion voltage for high-side N-channel MOSFET UVP current limit shut down with a 180 °
TRIP2
23
I
channel phase shift. Connect resistor between TRIP2 and GND for low-side N-channel MOSFET over current
latch shut-dow n. The oscillator voltage ramp adjustment (the feed-forward feature) for channel 2 is disabled
when this pin is tied to ground via a resistor.
VBST1
30
I
VBST2
VO1_VDDQ
16
5
I
I
Supply Input for high-side N-channel FET driver. Typically connected via charge pump from LLx.
Output discharge pin. Connect this pin to the SMPS output. The output is discharged to at least 0.3 V before
the channel can start-up again. If DDR is low, then the VO1_VDDQ pin must be connected to the VDDQ output
VO2
VREG5
11
22
I
O
since this pin works as the VDDQ feedback to generate the VTT reference voltage and VO2 should be con-
nected to GND since VTT must remain in a high-impedance state during S3 mode.
Internal, 60-mA, 5-V regulator output. DDR, ENBL1 or ENBL2 high ( > 2.2V) turns on the 5 V regulator.
High-voltage input. Typically the battery voltage. This pin serves as inputs for the VREF5 regulator, the REF_ X
VIN
24
I
re gulator and positive input for overcurrent comparators. Precaution should be taken for tracing between this
pin and the high-side N-channel MOSFET drain where positive node of TRIPx resistors are located.
Table 2. Reference Regulator Control
MODE
DDR
DDR
DDR
DDR
DUAL
DUAL
DUAL
DUAL
DDR
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
ENBL1
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
ENBL2
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
VREF5
OFF
ON
ON
ON
ON
ON
ON
ON
REF_X
OFF
OFF
VO1_DDR
2
VO1_DDR
2
OFF
10 V
10 V
10 V
OSC
OFF
ON
ON
ON
OFF
ON
ON
ON
8
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