参数资料
型号: TPS51217DSCR
厂商: Texas Instruments
文件页数: 15/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 10-SON
标准包装: 1
系列: D-CAP™
PWM 型: 控制器
输出数: 1
频率 - 最大: 368kHz
占空比: 89%
电源电压: 4.5 V ~ 6.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 10-WFDFN 裸露焊盘
包装: 标准包装
其它名称: 296-28856-6
SLUS947B – JUNE 2009 – REVISED APRIL 2012
POWER-GOOD
The TPS51217 has powergood output that indicates high when switcher output is within the target. The
powergood function is activated after soft-start has finished. If the output voltage becomes within +10%/–5% of
the target value, internal comparators detect power-good state and the power-good signal becomes high after a
1-ms internal delay. If the output voltage goes outside of +15%/–10% of the target value, the powergood signal
becomes low after a 2- μ s internal delay. The powergood output is an open-drain output and must be pulled up
externally.
CURRENT SENSE AND OVERCURRENT PROTECTION
TPS51217 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state
and the controller keeps the OFF state during the inductor current is larger than the overcurrent trip level. To
provide both good accuracy and cost effective solution, the TPS51217 supports temperature compensated
MOSFET R DS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor,
R (TRIP) . The TRIP terminal sources I (TRIP) current, which is 10 μ A typically at room temperature, and the trip level
is set to the OCL trip voltage V (TRIP) as shown in Equation 4 . Note that V (TRIP) is limited up to approximately 3 V
internally.
V (TRIP) (mV) = R (TRIP) (k ? ) × I (TRIP) ( μ A)
(4)
(4)
The inductor current is monitored by the voltage between GND pad and SW pin so that the SW pin should be
connected to the drain terminal of the low-side MOSFET properly. I (TRIP) has 4700ppm/°C temperature slope to
compensate the temperature dependency of the R DS(on) . GND is used as the positive current sensing node so
that GND should be connected to the proper current sensing device, i.e. the source terminal of the low-side
MOSFET.
As the comparison is done during the OFF state, V (TRIP) sets valley level of the inductor current. Thus, the load
current at overcurrent threshold, I OCP , can be calculated in Equation 5
V (TRIP) I IND ( ripple ) V (TRIP) 1 (V IN - V OUT ) ′ V OUT
? 8 ′ R DS(on) 2 8 ′ R DS(on) 2 ′ L ′ f SW IN
?                                ?
I OCP = ? ÷ + = + ′
è ?
÷ V
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down the
controller.
When the device is operating in the forced continuous conduction mode, the negative current limit (NCL) protects
the external FET from carrying too much current. The NCL detect threshold is set as the same absolute value as
positive OCL but negative polarity. Note that the forced continuous conduction mode appears only during the
Dynamic Voltage Step operation, and the threshold still represents the valley value of the inductor current.
OVER/UNDER VOLTAGE PROTECTION
TPS51217 monitors a resistor divided feedback voltage to detect over and undervoltage. When the feedback
voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit
latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins counting. After a 1-ms delay, TPS51217 latches OFF both high-
side and low-side MOSFETs drivers. This function is enabled after 1.2 ms following EN has become high.
DYNAMIC VOLTAGE STEP and PGOOD/OVP/UVP MASK
Output voltage of switcher can be dynamically step-up or step-down by controlling bottom resistance of the
output voltage divider. The simplest way is to add a MOSFET switch plus a resistor in parallel with the bottom
resistor. When the MOSFET switch is turned on, the VFB voltage is immediately dropped and comes back
equivalent to the internal reference voltage as the output voltage climbs up to match the new target. If the voltage
step is large, it may cause PGOOD state into 'bad' and also may hit UVP. In the case of voltage step-down, the
same PGOOD bad and OVP hit may happen. TRAN pin helps masking PGOOD, UVP and OVP during the
voltage transition. Combination of weighted capacitances C2 and C3 detect transition of VIDx ( Figure 22 ).
Masking of PGOOD, OVP and UVP start when the TRAN pin voltage goes outside of its window comparator
threshold. At this time, TRAN pin also starts sink or source current. 900 μ sec after TRAN pin voltage recovers
Copyright ? 2009–2012, Texas Instruments Incorporated
Product Folder Link(s) : TPS51217
15
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