参数资料
型号: TPS51217DSCR
厂商: Texas Instruments
文件页数: 18/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 10-SON
标准包装: 1
系列: D-CAP™
PWM 型: 控制器
输出数: 1
频率 - 最大: 368kHz
占空比: 89%
电源电压: 4.5 V ~ 6.5 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 10-WFDFN 裸露焊盘
包装: 标准包装
其它名称: 296-28856-6
SLUS947B – JUNE 2009 – REVISED APRIL 2012
3. Determine the value of R1 and R2.
The output voltage is programmed by the voltage-divider resistor, R1 and R2, shown in Figure 21 . R1 is
connected between the VFB pin and the output, and R2 is connected between the VFB pin and GND. Typical
designs begin with the selection of an R2 value between 10 k ? and 20 k ? . Determine R1 using Equation 9 .
? ? ÷ ÷ - 0.6
R1 =
? I IND(ripple) ′ ESR ?
V OUT -
2
è ?
0.6
′ R2
(9)
LAYOUT CONSIDERATIONS
VIN
TRIP
2
TPS51217
V5IN
6
1 10 m m F F
#1
V OUT
#2
VFB
4
5
DRVL
Thermal Pad
GND
#3
UDG-09066
Figure 24. Ground System of DC/DC Converter Using the TPS51217
Certain points must be considered before starting a layout work using the TPS51217.
?
?
?
Inductor, V IN capacitor(s), V OUT capacitor(s) and MOSFETs are the power components and should be placed
on one side of the PCB (solder side). Other small signal components should be placed on another side
(component side). At least one inner plane should be inserted, connected to ground, in order to shield and
isolate the small signal traces from noisy power lines.
All sensitive analog traces and components such as VFB, PGOOD, TRIP and TRAN should be placed away
from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to   avoid coupling. Use internal
layer(s) as ground plane(s) and shield feedback trace from power traces and   components.
The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the V IN capacitor(s) through the high and
low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the V IN
capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (See loop #1 of
– The second important loop is the path from the low-side MOSFET through inductor and V OUT capacitor(s),
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of V OUT capacitor(s) at ground as close as possible. (See loop #2 of Figure 24 )
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows
from gate of the low-side MOSFET through the gate driver and GND pad of the device, and back to
source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the
low-side MOSFET and GND pad of the device at ground as close as possible. (See loop #3 of Figure 24 )
18
Product Folder Link(s) : TPS51217
Copyright ? 2009–2012, Texas Instruments Incorporated
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