参数资料
型号: TPS51916EVM-746
厂商: Texas Instruments
文件页数: 15/34页
文件大小: 0K
描述: EVAL MODULE FOR TPS51916-746
标准包装: 1
系列: D-Cap™, D-Cap2™
主要目的: 特殊用途 DC/DC,DDR 存储器电源
输出及类型: 1,非隔离
输出电压: 1.2 V ~ 1.5 V
电流 - 输出: 20A
输入电压: 8 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 500kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: TPS51916
其它名称: 296-30054
TPS51916EVM-746-ND

TPS51916
SLUSAE1D – DECEMBER 2010 – REVISED JUNE 2012
APPLICATION INFORMATION
VDDQ Switch Mode Power Supply Control
The TPS51916 supports two SMPS control architectures, D-CAP? mode and D-CAP2? mode. Both control
modes do not require complex external compensation networks and are suitable for designs with small external
components counts. The D-CAP? mode provides fast transient response with appropriate amount of equivalent
series resistance (ESR) on the output capacitors. The D-CAP2? mode is dedicated for a configuration with very
low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). For the both modes, an adaptive on-
time control scheme is used to achieve pseudo-constant frequency. The TPS51916 adjusts the on-time (t ON ) to
be inversely proportional to the input voltage (V IN ) and proportional to the output voltage (V VDDQ ). This makes a
switching frequency fairy constant over the variation of input voltage at the steady state condition. These control
modes and switching frequencies are selected by the MODE pin described in Table 2 .
VREF and REFIN, VDDQ Output Voltage
The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300- μ A (max)
current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of
0.1- μ F or larger should be attached close to the VREF terminal.
The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range
between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External
Components Selection section.) A few nano farads of capacitance from REFIN to GND is recommended for
stable operation.
Soft-Start and Powergood
Provide a voltage supply to VIN and V5IN before asserting S5 to high. TPS51916 provides integrated VDDQ
soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal
reference voltage ramping up. Figure 34 shows the start-up waveforms. The switching regulator waits for 400 μ s
after S5 assertion. The MODE pin voltage is read in this period. A typical VDDQ ramp up duration is 700 μ s.
TPS51916 has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The
target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for
assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The
PGOOD start-up delay is 2.5 ms after S5 is asserted to high. Note that the time constant which is composed of
the REFIN capacitor and a resistor divider needs to be short enough to reach the target value before PGOOD
comparator enabled.
S5
VREF
VDDQ
PGOOD
400 m s
700 m s
1.4 ms
UDG-10137
Figure 34. Typical Start-up Waveforms
Copyright ? 2010–2012, Texas Instruments Incorporated
15
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