参数资料
型号: TPS51916EVM-746
厂商: Texas Instruments
文件页数: 17/34页
文件大小: 0K
描述: EVAL MODULE FOR TPS51916-746
标准包装: 1
系列: D-Cap™, D-Cap2™
主要目的: 特殊用途 DC/DC,DDR 存储器电源
输出及类型: 1,非隔离
输出电压: 1.2 V ~ 1.5 V
电流 - 输出: 20A
输入电压: 8 ~ 20 V
稳压器拓扑结构: 降压
频率 - 开关: 500kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: TPS51916
其它名称: 296-30054
TPS51916EVM-746-ND
TPS51916
SLUSAE1D – DECEMBER 2010 – REVISED JUNE 2012
D-CAP? Mode
Figure 35 shows a simplified model of D-CAP? mode architecture.
V IN
VDDQSNS
9
14
DRVH
High-Side
MOSFET
REFIN
R1 VREF
8
PWM
+
Control
Logic
and
Driver
Lx
VDDQ
ESR
R LOAD
6
DRVL
Low-Side
R2
+
1.8 V
11
MOSFET
C OUT
f 0 = £ SW
UDG-10136
Figure 35. Simplified D-CAP? Model
The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on
the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the
beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage
monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase. The D-CAP? mode offers flexibility on output inductance and capacitance selections with ease-of-use
without complex feedback loop calculation and external components. However, it does require a sufficient level
of ESR that represents inductor current information for stable operation and good jitter performance. Organic
semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended.
The requirement for loop stability is simple and is described in Equation 1 . The 0-dB frequency, f 0 defined in
Equation 1 , is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.
1 f
2 p ′ ESR ′ C OUT 3
where
?
?
ESR is the effective series resistance of the output capacitor
C OUT is the capacitance of the output capacitor
?
f sw is switching frequency
(1)
Copyright ? 2010–2012, Texas Instruments Incorporated
17
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