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参数资料
| 型号： | TPS54110PWP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 3.5 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | GREEN, PLASTIC, HTSSOP-20 |
| 文件页数： | 14/30页 |
| 文件大小： | 870K |
| 代理商： | TPS54110PWP |
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SLVS500C
– DECEMBER 2003 – REVISED FEBRUARY 2011
Overcurrent Protection
Cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off
within 200 ns of reaching the current-limit threshold. A 100-ns leading-edge blanking circuit prevents false
tripping of the current limit. Current-limit detection occurs only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current-sink operation is provided by thermal shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150
°C. The device is released from shutdown when the junction temperature decreases to
10
°C below the thermal-shutdown trip point, and starts up under control of the slow-start circuit. Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. In a
persistent-fault condition, the device cycles continuously; starting up under control of the soft-start circuit, heating
up due to the fault, and then shutting down upon reaching the thermal-shutdown point.
Power Good (PWRDG)
The power-good circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 7% below
the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than
the UVLO threshold, or SS/ENA is low, or if thermal shutdown asserts. When VIN = UVLO threshold, SS/ENA =
enable threshold, and VSENSE
> 93% of Vref, the open-drain output of the PWRGD pin is high. A hysteresis
voltage equal to 3% of Vref and a 35-s falling-edge deglitch circuit prevent tripping of the power-good
comparator due to high frequency noise.
PCB Layout Considerations
The VIN pins are connected together on the printed board (PCB) and bypassed with a low-ESR ceramic bypass
capacitor. Minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54110
ground pins. The recommended bypass capacitor is 10-
μF (minimum) ceramic with X5R or X7R dielectric. The
optimum placement is closest to the VIN pins and the AGND and PGND pins. See Figure 31 for an example
layout. It has an area of ground on the top layer directly under the IC, with an exposed area for connection to the
PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground
side of the input and output filter capacitors as well. Tie the AGND and PGND pins to the PCB ground area
under the device as shown. Use a separate wide trace for the analog-ground path, connecting the voltage
set-point divider, timing resistor RT, slow-start capacitor and bias-capacitor grounds. Tie the PH pins together
and route to the output inductor. Since the PH connection is the switching node, locate the inductor very close to
the PH pins, and minimize the area of the conductor to prevent excessive capacitive coupling. Connect the boot
capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and
minimize the conductor trace lengths. Connect the output-filter capacitor(s) as shown between the VOUT trace
and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout and PGND as small as is practical.
Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of the IC package and the device pin-out, they must be
somewhat closely routed while maintaining as much separation as possible, yet keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency,
connect them to this trace as well.
2003–2011, Texas Instruments Incorporated
21
Product Folder Link(s): TPS54110
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| TPS54110PWPG4 | 功能描述:直流/直流开关调节器 1.5A Step Down Converter RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| TPS54110PWPR | 功能描述:直流/直流开关调节器 1.5A Step Down Converter RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| TPS54110PWPRG4 | 功能描述:直流/直流开关调节器 1.5A Step Down Converter RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
| TPS54110-Q1 | 制造商:TI 制造商全称:Texas Instruments 功能描述:3-V TO 6-V INPUT, 1.5-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT?￡a) |
| TPS54110QPWPRQ1 | 功能描述:直流/直流开关调节器 3-6V Input 1.5A Out Synch Buck PWM Swer RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
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