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参数资料
| 型号： | TPS54110PWP |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 3.5 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | GREEN, PLASTIC, HTSSOP-20 |
| 文件页数： | 26/30页 |
| 文件大小： | 870K |
| 代理商： | TPS54110PWP |
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1
2
3
4
5
6
7
8
9
10
20
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18
17
16
15
14
13
12
11
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
SYNC
SS/ENA
VBIAS
VIN
PGND
SLVS500C
– DECEMBER 2003 – REVISED FEBRUARY 2011
PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground
—internally connected to the sensitive analog-ground circuitry. Connect to PGND and PowerPAD.
Bootstrap input. 0.022-
F to 0.1-F low-ESR capacitor connected from BOOT to PH generates floating drive for the
BOOT
5
high-side FET driver.
COMP
3
Error amplifier output. Connect compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
PGND
11
–13
areas to the input and output supply returns, and negative terminals of the input and output capacitors. Connect to
AGND and PowerPAD.
PH
6
–10
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power-good open drain output. High when VSENSE
≥ 93% Vref, otherwise PWRGD is low. Note that output is low
PWRGD
4
when SS/ENA is low or internal shutdown signal active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
Slow-start/enable input/output. Dual-function pin that provides logic input to enable/disable device operation and
SS/ENA
18
capacitor input to externally set the start-up time.
Synchronization input. Dual-function pin that provides logic input to synchronize to an external oscillator or pin select
SYNC
19
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
VBIAS
17
high quality, low ESR 0.1-
F to 1.0-F ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
VIN
14
–16
device package with a high quality, low ESR 1-
F to 10-F ceramic capacitor.
VSENSE
2
Error amplifier inverting input.
2003–2011, Texas Instruments Incorporated
5
Product Folder Link(s): TPS54110
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