![](http://datasheet.mmic.net.cn/130000/TPS54110PWP_datasheet_5022222/TPS54110PWP_12.png)
LC
R
C
1
3 =
p 6
1
8 =
2p 1LC
C
R
0
1
=
2p
ESR
OUT
R
C
1
5 =
2p 8ESR
R
C
CO
8 R3
1
7 =
p
C
OUT
R1
0.891
R2
V
-0.891
=
SLVS500C
– DECEMBER 2003 – REVISED FEBRUARY 2011
The first zero, fZ1 is located at one half the output filter LC corner frequency, so R3 is calculated from:
(19)
The second zero, fZ2 is located at the output filter LC corner frequency, so C8 is calculated from:
(20)
The first pole, fP1 is located to coincide with output filter ESR zero frequency. This frequency is given by:
(21)
where RESR is the equivalent series resistance of the output capacitor.
In this case, the ESR zero frequency is 35.4 kHz, and R5 is calculated from:
(22)
The final pole is placed at a frequency high enough above the closed-loop crossover frequency to avoid causing
an excessive phase decrease at the crossover frequency while still providing enough attenuation so that there is
little or no gain at the switching frequency. The fP2 pole location for this circuit is set to 4 times the closed-loop
crossover frequency and the last compensation component value C7 is derived:
(23)
Finally, calculate the R2 resistor value for the output voltage of 3.3 V using
Equation 24:(24)
For this TPS54110 design, use R1 = 10.7 k
Ω instead of 10.0 kΩ. R2 is then 3.92 kΩ.
Since capacitors are only available in a limited range of standard values, the nearest standard value was chosen
for each capacitor. The measured closed-loop response for this design is shown in
Figure 19.BIAS and Bootstrap Capacitors
Every TPS54110 design requires a bootstrap capacitor (C3), and a bias capacitor (C4). The bootstrap capacitor
must be between 0.022
F and 0.1 F. This design uses 0.047 F. The bootstrap capacitor is located between
the PH pins and BOOT. The bias capacitor is connected between the VBIAS pin and AGND. Recommended
values are 0.1
F to 1.0 F. This design uses 0.1 F. Use high-quality ceramic capacitors with X7R or X5R
grade dielectric for temperature stability. Place them as close to the device pins as possible.
Grounding and PowerPAD Layout
The TPS54110 has two internal grounds (analog and power). Inside the TPS54110, the analog ground connects
all noise-sensitive signals, while the power ground connects the noisier power signals. The PowerPAD must be
tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54110,
particularly at higher output currents. However, ground noise on an analog ground plane can also cause
problems with some of the control and bias signals. For these reasons, separate analog and power ground
planes are recommended. Tie these two planes together directly at the IC to reduce noise between the two
grounds. The only components that tie directly to the power-ground plane are the input capacitor, the output
capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54110. The layout of the
TPS54110 evaluation module represents recommended layout for a 2-layer board. Documentation for the
TPS54110 evaluation module is obtained from the Texas Instruments web site under the TPS54110 product
folder and in the application note, TI literature number
SLVA109.12
2003–2011, Texas Instruments Incorporated