DETAILED DESCRIPTION
Fixed Frequency PWM Control
Slope Compensation Output Current
Pulse Skip Eco-Mode
VOUT(ac)
IL
PH
Bootstrap Voltage (BOOT)
SLVS889 – OCTOBER 2008 .............................................................................................................................................................................................. www.ti.com
The TPS54140 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output
is compared to the high side power switch current. When the power switch current reaches the COMP voltage
level the power switch is turned off. The COMP pin voltage will increase and decrease as the output current
increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-Mode is implemented with a minimum clamp on the COMP pin.
The TPS54140 adds a compensating ramp to the switch current signal. This slope compensation prevents
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
The TPS54140 enters the pulse skip mode when the voltage on the COMP pin is the minimum clamp value. The
TPS54140 operates in a pulse skip mode at light load currents to improve efficiency. The peak switch current
during the pulse skip mode will be the greater value of 50mA or the peak inductor current that is a function of the
minimum on time, input voltage, output voltage and inductance value. When the load current is low and the
output voltage is within regulation the device will enter a sleep mode and draw only 116
A input quiescent
current. While the device is in sleep mode the output power is delivered by the output capacitor. As the load
current decreases, the time the output capacitor supplies the load current increases and the switching frequency
decreases reducing gate drive and switching losses. As the output voltage drops, the TPS54140 wakes up from
the sleep mode and the power switch turns on to recharge the output capacitor, see
Figure 25. The internal PLL
remains operating when in sleep mode. When operating at light load currents in the pulse skip mode the
switching transitions occur synchronously with the external clock signal.
Figure 25. Pulse Skip Mode Operation
The TPS54140 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be
0.1
F. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage. To improve drop out, the TPS54140 is designed to operate at
12
Copyright 2008, Texas Instruments Incorporated