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参数资料
| 型号： | TPS54240QDGQRQ1 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 2.5 A SWITCHING REGULATOR, 2500 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封装： | GREEN, PLASTIC, MSOP-10 |
| 文件页数： | 28/48页 |
| 文件大小： | 1447K |
| 代理商： | TPS54240QDGQRQ1 |
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Cout
Vout
0.8
Tss >
Issavg
SLVSAQ4A
– DECEMBER 2010 – REVISED APRIL 2011
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow start current of Issavg. In the example, to charge the effective output capacitance of 72.4
F up to 3.3V
while only allowing the average output current to be 1 A would require a 0.19 ms slow start time.
Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the
example circuit, the slow start time is not too critical since the output capacitor value is 2 x 47
μF which does not
require much current to charge to 3.3V. The example circuit has the slow start time set to an arbitrary value of
3.5 ms which requires a 8.75 nF slow start capacitor. For this design, the next larger standard value of 10 nF is
used.
(40)
Bootstrap Capacitor Selection
A 0.1-
μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is
recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V
or higher voltage rating.
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54240-Q1. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply should turn on
and start switching once the input voltage increases above 6.0 V (enabled). After the regulator starts switching, it
should continue to do so until the input voltage falls below 5.5 V (UVLO stop).
The programmable UVLO and enable voltages are set using the resistor divider of R1 and R2 between Vin and
ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary.
For the example application, a 124 k
between Vin and EN (R1) and a 30.1 k between EN and ground (R2)
are required to produce the 6.0 and 5.5 volt start and stop voltages.
Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 is used to set the output voltage. For the example design, 10.0 k
was
selected for R6. Using Equation 1, R5 is calculated as 31.25 k
. The nearest standard 1% resistor is 31.6 k.
Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater
than 1
μA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R2
equal to 800 k
. Choosing higher resistor values will decrease quiescent current and improve efficiency at low
output currents but may introduce noise immunity problems.
Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assumes the crossover frequency is between the modulator pole and the
esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and
Equation 42. For Cout, use a derated value of 40
μF. Use equations Equation 43 and Equation 44, to estimate a
starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
1206 Hz and fzmod is 530.5 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 25.3 kHz and
Equation 44 gives 13.4 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, a higher fco is desired to improve transient response. the target fco is 35.0 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole.
34
Copyright
2010–2011, Texas Instruments Incorporated
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