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| 型号： | TPS54478RTET |
| 厂商： | Texas Instruments |
| 文件页数： | 31/38页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 16WQFN |
| 标准包装： | 1 |
| 系列： | SWIFT™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 4.5 V |
| 输入电压： | 2.95 V ~ 6 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-WQFN 裸露焊盘（3x3） |
| 其它名称： | 296-29064-6 |
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SLVSAS2 – JUNE 2011
So
Ptot = Pcon + Pd + Psw + Pgd + Pq
For given TA,
TJ = TA + Rth × Ptot
For given TJMAX = 150 ° C
TAmax = TJ max – Rth × Ptot
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature ( ° C).
TJ is the junction temperature ( ° C).
Rth is the thermal resistance of the package ( ° C/W).
TJMAX is maximum junction temperature ( ° C).
TAMAX is maximum ambient temperature ( ° C).
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
LAYOUT
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the
bypass capacitor connections and the VIN pins. See Figure 53 for a PCB layout example. The GND pins and
AGND pin should be tied directly to the power pad under the IC. The power pad should be connected to any
internal PCB ground planes using multiple vias directly under the IC. Additional vias can be used to connect the
top side ground area to the internal planes near the input and output capacitors. For operation at full rated load,
the top side ground area along with any additional internal ground planes must provide adequate heat dissipating
area.
Locate the input bypass capacitor as close to the IC as possible. The PH pin should be routed to the output
inductor. Since the PH connection is the switching node, the output inductor should be located very close to the
PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The boot
capacitor must also be located close to the device. The sensitive analog ground connections for the feedback
voltage divider, compensation components, slow start capacitor and frequency set resistor should be connected
to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor
should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external
components can be placed approximately as shown. It may be possible to obtain acceptable performance with
alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.
Copyright ? 2011, Texas Instruments Incorporated
31
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