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参数资料
| 型号： | TPS54623RHLT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 15 A SWITCHING REGULATOR, 1760 kHz SWITCHING FREQ-MAX, PQCC14 |
| 封装： | 3.50 X 3.50 MM, GREEN, PLASTIC, QFN-14 |
| 文件页数： | 21/35页 |
| 文件大小： | 1468K |
| 代理商： | TPS54623RHLT |
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V
= 2 V / div
OUT
PH = 10 V / div
Inductor Current = 5 A / div
Time = 20 msec / div
50
55
60
65
70
75
80
85
90
95
100
0.01
0.1
1
10
Output Current - A
Ef
ficiency
-
%
Vin = 8 V
Vin = 12 V
Vin = 17 V
SLVSB09
– SEPTEMBER 2011
EFFICIENCY
vs
OUTPUT CURRENT
TPS54623 Hiccup Mode Current Limit
Figure 46.
Figure 47.
Fast Transient Considerations
In applications where fast transient responses are very important, Type III frequency compensation can be used
instead of the traditional Type II frequency compensation.
For more information about Type II and Type III frequency compensation circuits, see Designing Type III
PCB Layout Guidelines
Layout is a critical portion of good power supply design. See Figure 48 for a PCB layout example. The top layer
contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the
remaining pins of the TPS54623 and a large top side area filled with ground. The top layer ground area should
be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor
and directly under the TPS54623 device to provide a thermal path from the exposed thermal pad land to ground.
The GND pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated
load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating
area. There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor
with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a
low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quite analog
ground trace rather than the power ground trace of the PVIn bypass capacitor. Since the PH connection is the
switching node, the output inductor should be located close to the PH pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same
power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining
adequate width. The small signal components should be grounded to the analog ground path as shown. The
RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed
with minimal lengths of trace. The additional external components can be placed approximately as shown. It may
be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to
produce good results and is meant as a guideline.
Land pattern and stencil information is provided in the data sheet addendum. The dimension and outline
information is for the standard RHL (S-PVQFN-N14) package. There may be slight differences between the
provided data and actual lead frame used on the TPS54623RHL package.
28
Copyright
2011, Texas Instruments Incorporated
Product Folder Link(s) :TPS54623
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