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参数资料
| 型号： | TPS62650YFFR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 1.7 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, BGA9 |
| 封装： | GREEN, DSBGA-9 |
| 文件页数： | 33/38页 |
| 文件大小： | 820K |
| 代理商： | TPS62650YFFR |
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SLVS808A
– AUGUST 2009 – REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and
TA = -40°C to 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at
VI = 3.6V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING
Setup Time Between
Rising EN and Start of
TPS62650/1
50
μs
I2C Stream
Output voltage settling
From min to max output voltage,
VO
TPS62650/1
12
μs
time
IO(DC) = 500 mA, VSEL = VI, PWM operation
Time from active EN to VO
125
VO = 1.2 V, IO = 0 mA, PWM operation
Start-up time
TPS62650/1
μs
Time from active EN to VO
120
VO = 1.05 V, IO = 0 mA, PFM operation
I
2C INTERFACE TIMING CHARACTERISTICS(1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Standard mode
100
kHz
Fast mode
400
kHz
Fast mode plus
1
MHz
f(SCL)
SCL Clock Frequency
High-speed mode (write operation), CB – 100 pF max
3.4
MHz
High-speed mode (read operation), CB – 100 pF max
3.4
MHz
High-speed mode (write operation), CB – 400 pF max
1.7
MHz
High-speed mode (read operation), CB – 400 pF max
1.7
MHz
Standard mode
4.7
μs
Bus Free Time Between a STOP and
tBUF
Fast mode
1.3
μs
START Condition
Fast mode plus
0.5
μs
Standard mode
4
μs
Fast mode
600
ns
Hold Time (Repeated) START
tHD, tSTA
Condition
Fast mode plus
260
ns
High-speed mode
160
ns
Standard mode
4.7
μs
Fast mode
1.3
μs
tLOW
LOW Period of the SCL Clock
Fast mode plus
0.5
μs
High-speed mode, CB – 100 pF max
160
ns
High-speed mode, CB – 400 pF max
320
ns
Standard mode
4
μs
Fast mode
600
ns
tHIGH
HIGH Period of the SCL Clock
Fast mode plus
260
ns
High-speed mode, CB – 100 pF max
60
ns
High-speed mode, CB – 400 pF max
120
ns
Standard mode
4.7
μs
Fast mode
600
ns
Setup Time for a Repeated START
tSU, tSTA
Condition
Fast mode plus
260
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
tSU, tDAT Data Setup Time
Fast mode plus
50
ns
High-speed mode
10
ns
(1)
Specified by design. Not tested in production.
4
2009–2011, Texas Instruments Incorporated
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