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参数资料
| 型号： | TPS62650YFFR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 1.7 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, BGA9 |
| 封装： | GREEN, DSBGA-9 |
| 文件页数： | 36/38页 |
| 文件大小： | 820K |
| 代理商： | TPS62650YFFR |
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TPS6265x
CSP9
(TOP VIEW)
A3
B3
C3
A2
B2
C2
A1
B1
C1
TPS6265x
CSP9
(BOTTOMVIEW)
A1
B1
C1
A2
B2
C2
A3
B3
C3
GateDriver
Anti
Shoot-Through
PowerSaveMode
SwitchingLogic
+
-
Frequency
Control
FB
SW
Soft-Start
EN
VIN
CurrentLimit
Detect
Undervoltage
Lockout
BiasSupply
Bandgap
Thermal
Shutdown
NegativeInductor
CurrentDetect
VIN
V
= 0.75 V
REF
VDAC
VSEL
SDA
SCL
GND
6-Bit
DAC
Control
Logic
Registers
I CI/F
2
SLVS808A
– AUGUST 2009 – REVISED FEBRUARY 2011
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
VIN
A2
I
This is the input voltage pin of the device. Connect directly to the input bypass capacitor.
This is the enable pin of the device. Connect this pin to ground forces the device into
shutdown mode. Pulling this pin to VI enables the device. On the rising edge of the enable
EN
B3
I
pin, all the registers are reset with their default values. This pin must not be left floating and
must be terminated.
VSEL signal is primarily used to scale the output voltage and to set the TPS6265x operation
between active mode (VSEL=HIGH) and sleep mode (VSEL=LOW). The mode of operation
VSEL
A1
I
can also be adapted by I2C settings. This pin must not be left floating and must be
terminated.
SDA
A3
I/O
Serial interface address/data line.
SCL
B2
I
Serial interface clock line.
FB
C1
I
Output feedback sense input. Connect FB to the converter output.
GND
C2, C3
Ground.
This is the switch pin of the converter and connected to the drain of the internal power
SW
B1
I/O
MOSFETs.
FUNCTIONAL BLOCK DIAGRAM
2009–2011, Texas Instruments Incorporated
7
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