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参数资料
| 型号： | TPS65014RGZT |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封装： | 7 X 7 MM, GREEN, PLASTIC, VQFN-48 |
| 文件页数： | 21/57页 |
| 文件大小： | 1289K |
| 代理商： | TPS65014RGZT |
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TPS65014 Power States Description
TPS65014
SLVS551 – DECEMBER 2004
State 1: No Power
No batteries are connected to the TPS65014. When main power is applied, the bandgap reference, LDOs, and
UVLO comparator start up. The RESPWRON, PWRFAIL, INT and MPU_RESET signals are held low. When
BATT_COVER goes high (de-bounced internally by the TPS65014), indicating that the battery cover has been
put in place and if VCC > UVLO, the power supplies are ramped in the sequence defined by PS_SEQ.
RESPWRON, PWRFAIL, INT, and MPU_RESET are released when the RESPWRON timer has timed out after
tn(RESPWRON) seconds. If VCC remains valid and no OVERTEMP condition occurs, then the TPS65014 arrives in
State 2: ON. If VCC < UVLO, the TPS65014 keeps the bandgap reference and UVLO comparator active such
that when VCC>UVLO (during battery charge), the supplies are automatically activated.
State 2: ON
In this state, the TPS65014 is fired up and ready for operation. The switching converter output voltages can be
programmed. The LDOs can be disabled or programmed. The TPS65014 can exit this state due to an
overtemperature condition, an undervoltage condition at VCC, BATT_COVER going low, or by the processor
programming low power mode. State 2 is left temporarily if the user activates the HOT_RESET pin.
State 3: Low Power Mode
This state is entered via the processor setting the ENABLE_LP bit in the serial interface and then raising the
LOW_PWR pin. The TPS65014 actually uses the rising edge of the internal signal formed by a logical AND of
the LOW_PWR and ENABLE LP signals to enter low power mode. The VMAIN switching converter remains
active, but the VCORE converter may be disabled in low power mode through the serial interface by setting the
LP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltage is set to the value predefined by
the CORELP0/1 bits in the VDCDC2 register. The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1
register determine whether the LDOs are turned off or put in a reduced power mode (transient speed-up circuitry
disabled in order to minimize quiescent current) in low power mode. All TPS65014 features remain addressable
through the serial interface. TPS65014 can exit this state either due to an undervoltage condition at VCC, due to
BATT_COVER going low, due to an OVERTEMP condition, by the processor de-asserting the LOW_POWER
pin, or by the user activating the HOT_RESET pin or the PB_ONOFF pin.
State 4: Shutdown
There are two scenarios for entering this state. The first is from State 1: No Power. As soon as main battery
power is applied, the device automatically enters the WAIT mode.
The second scenario occurs when the device is in ON mode and the processor initiates a shutdown by resetting
the ENABLE SUPPLY bit in the VDCDC1 register (ENABLE_LP must be high), and then raising the LOW_PWR
pin. When this happens, the power rails are ramped down in the predefined sequence, and all circuitry is then
disabled. In this state, the TPS65014 waits for the PB_ONOFF or HOT_RESET pin to be activated before
enabling any of the supply rails. When the PB_ONOFF or HOT_RESET pin is activated, the TPS65014 powers
up the supplies according to the same constraints as at the initial application of power. Complete shutdown is
only achieved by setting the LDO1OFF/nSLP and LDO2OFF/nSLP bits high in the VREGS1 register before
activating the shutdown.
In this case, the I
2C interface is deactivated, and the registers are reset to their default value after leaving the
WAIT mode.
To enter the WAIT mode when USB or AC is present, the AUA bit (CHCONFIG<7>) must be set. The WAIT
mode is automatically left if bit 7 in register CHCONFIG is set to 0 (default), and a voltage is present at either the
AC pin or the USB pin in the appropriate range for charging, and the voltage at VCC is above the UVLO
threshold. This feature allows the converters to start up automatically if the device is plugged in for charging.
If all supplies are turned off in WAIT mode, the internal bandgap is switched off, and the internal registers are
reset to their default state when the device returns to ON mode.
Table 2 shows possible configurations in LOW POWER mode and WAIT mode.
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