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参数资料
| 型号： | TPS650531RGER |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 5-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24 |
| 封装： | 4 X 4 MM, 0.50 MM PITCH, GREEN, PLASTIC, QFN-24 |
| 文件页数： | 4/27页 |
| 文件大小： | 858K |
| 代理商： | TPS650531RGER |
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DETAILED DESCRIPTION
OPERATION
POWER SAVE MODE
I
PFM_enter +
VIN
DCDC
32 W
(1)
I
PFM_leave +
VIN
DCDC
24 W
(2)
SLVS754C – MARCH 2007 – REVISED SEPTEMBER 2009 ............................................................................................................................................. www.ti.com
The TPS65053x include two synchronous step-down converters. The converters operate with 2.25MHz fixed
frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents the
converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation).
During PWM operation the converters use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is
turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
The current limit comparator will also turn off the switch in case the current limit of the P-channel switch is
exceeded. After the adaptive dead time prevents shoot through current, the N-channel MOSFET rectifier is
turned on and the inductor current ramps down. The next cycle is initiated by the clock signal again turning off
the N-channel rectifier and turning on the P-channel switch.
The two DC-DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase
shift between Converter 1 and Converter 2 decreases the input RMS current. Therefore smaller input capacitors
can be used.
The converters output voltage is set by an external resistor divider connected to FB_DCDC1 or FB_DCDC2,
respectively. See application section for more details.
The Power Save Mode is enabled with Mode Pin set to low. If the load current decreases, the converters will
enter Power Save Mode operation automatically. During Power Save Mode the converters operate with reduced
switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The
converter will position the output voltage typically 1% above the nominal output voltage. This voltage positioning
feature minimizes voltage drops caused by a sudden load step.
In order to optimize the converter efficiency at light load the average current is monitored and if in PWM mode
the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold
can be calculated according to:
Equation 1: Average output current threshold to enter PFM mode.
Equation 2: Average output current threshold to leave PFM mode.
During the Power Save Mode the output voltage is monitored with a comparator. As the output voltage falls
below the skip comparator threshold (skip comp) of VOUTnominal +1%, the P-channel switch will turn on and the
converter effectively delivers a constant current as defined above. If the load is below the delivered current then
the output voltage will rise until the same threshold is crossed again, whereupon all switching activity ceases,
hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold
again. If the load current is greater than the delivered current then the output voltage will fall until it crosses the
skip comparator low (Skip Comp Low) threshold set to 1% below nominal Vout, whereupon Power Save Mode is
exited and the converter returns to PWM mode.
These control methods reduce the quiescent current typically to 12
A per converter and the switching frequency
to a minimum thereby achieving the highest converter efficiency. The PFM mode operates with very low output
voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing
capacitor values will make the output ripple tend to zero.
The Power Save Mode can be disabled by driving the MODE pin high. Both converters will operate in fixed PWM
mode. Power Save Mode Enable/Disable applies to both converters.
12
Copyright 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS65053 TPS650531 TPS650532
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| TPS650531RGET | 功能描述:PMIC 解决方案 5Ch Pwr Mgmt IC w/2 Step-Down Converters RoHS:否 制造商:Texas Instruments 安装风格:SMD/SMT 封装 / 箱体:QFN-24 封装:Reel |
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