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参数资料
| 型号： | TPS65055RSMR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 稳压器 |
| 英文描述： | 1.8 A DUAL SWITCHING CONTROLLER, 2475 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封装： | 4 X 4 MM, GREEN, PLASTIC, QFN-32 |
| 文件页数： | 10/41页 |
| 文件大小： | 1276K |
| 代理商： | TPS65055RSMR |
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POWER SAVE MODE
DCDC
PFM_enter
VIN
I
=
32 W
DCDC
PSMDCDCleave
VIN
I
=
24 W
Dynamic Voltage Positioning
SLVS844 – SEPTEMBER 2008.......................................................................................................................................................................................... www.ti.com
The DEFDCDC2 pin can either be connected to GND, or to VCC. The converter 2 defaults to 1.0 V or 1.2 V
depending on the logic level of the DEFDCDC2 pin. If DEFDCDC2 is tied to ground, the default is 1.2 V; if it is
tied to VCC, the default is 1.0 V.
With the TPS65055, the voltage can also be changed using the I2C registers – see the application section for
details.
Power safe mode is enabled per default and can be disabled using the I2C compatible interface. If the load
current decreases, the converters enter power save mode operation automatically. During power save mode the
converters operate with reduced switching frequency in PFM mode and with a minimum quiescent current to
maintain high efficiency. The converter positions the output voltage typically 1% above the nominal output
voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step.
In order to optimize converter efficiency at light load the average current is monitored, and if in PWM mode the
inductor current remains below a certain threshold, then power save mode is entered. The typical threshold can
be calculated according to:
Equation 1: Average output current threshold to enter PFM mode
Equation 2: Average output current threshold to leave PFM mode
During power save mode, the output voltage is monitored with a comparator. As the output voltage falls below
the skip comparator threshold (skip comp) of VOUTnominal +1%, the P-channel switch turns on and the converter
effectively delivers a constant current as defined above. If the load is below the delivered current, then the output
voltage rises until the same threshold is crossed again, whereupon all switching activity ceases, hence reducing
the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load
current is greater than the delivered current, then the output voltage falls until it crosses the skip comparator low
(skip comp low) threshold set to 1% below nominal Vout, whereupon power save mode is exited and the
converter returns to PWM mode.
These control methods reduce the quiescent current typically to 12
A per converter and the switching frequency
to a minimum achieving the highest converter efficiency. PFM mode operates with very low output voltage ripple.
The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values
makes the output ripple tend to zero.
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
activated in power save mode operation when the converter runs in PFM mode. It provides more headroom for
both, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transient
behavior.
At light loads, in which the converter operates in PFM mode, the output voltage is regulated typically 1% higher
than the nominal value. In case of a load transient from light load to heavy load, the output voltage drops until it
reaches the skip comparator low threshold set to –1% below the nominal value and enters PWM mode. During a
load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation
turning on the N-channel switch.
18
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS65055
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