
||
+
-
-
÷
è
S_HVS
FB
S_HVS
FB
R1 R2 R12
R1 R2
V
= V
R12 =
V
R2 R12
1
R2 R1
V
FB
R1
R2
V
S
R12
W
-
÷
÷
è
REG_FB
REG_O
REG_FB
V
R11 =
18 k
R10 = R11
1
70 A
V
REG_FB
R10
R11
V
REG_O
www.ti.com
SLVS904A – MAY 2009 – REVISED JANUARY 2011
Over Current Protection (OCP)
If the FB voltage is below 90% of its typical value (1.240 V) for more than 55 ms, the GD pin is pulled 'high' and
the device latched down. The input voltage VIN needs to be cycled to restart the device.
HIGH VOLTAGE STRESS (HVS) FOR THE BOOST CONVERTER
The TPS65148 incorporates a High Voltage Stress test enabled by pulling the logic pin HVS 'high'. The output
voltage of the boost converter VS is then set to a higher output voltage compared to the nominal programmed
output voltage. If unregulated external charge pumps are connected via the boost converter, their outputs will
increase as VS increases. This stress voltage is flexible and set by the resistor connected to RHVS pin. With
HVS = 'high' the RHVS pin is pulled to GND. The external resistor connected between FB and RHVS (as shown
in
Figure 19) is therefore put in parallel to the low-side resistor of the boost converter's feedback divider. The
output voltage for the boost converter during HVS test is calculated as:
with VFB = 1.240 V
(8)
If the VGH voltage needs to be set to a higher value by using the HVS test, VGH must be connected to VGH pin
without a regulation stage. The VGH voltage will then be equal to VS_HVS times 2 or 3 (depending if a doubler or
tripler mode is used for the external positive charge pump). The same circuit changes can be held on the
negative charge pump as well if required.
CAUTION
Special caution must be taken in order to limit the voltage on the VGH pin to 35V
(maximum recommended voltage).
VOLTAGE REGULATOR FOR GAMMA BUFFER
TPS65148 includes a voltage regulator (Low Dropout Linear Regulator, LDO) to supply the Gamma Buffer with a
very stable voltage. The LDO is designed to operate typically with a 4.7 F ceramic output capacitor (any value
between 1 F and 15 F works properly) and a ceramic bypass capacitor of minimum 1 F on its input REG_I
connected to ground. The output of the boost converter VS is usually connected to the input REG_I. The LDO
has an internal softstart feature of 2 ms maximum to limit the inrush current. As for the boost converter, a
minimum current of 50 A flowing through the feedback divider is usually enough to cover the noise fluctuation.
The resistors are then calculated with 70 A as:
with VREG_FB = 1.240 V
(9)
VCOM BUFFER
The VCOM Buffer power supply pin is the SUP pin connected to the boost converter VS. To achieve good
performance and minimize the output noise, a 1 mF ceramic bypass capacitor is required directly from the SUP
pin to ground. The input positive pin OPI is either supplied through a resistive divider from VS or from an external
PMIC. The buffer is not designed to drive high capacitive loads; therefore it is recommended to connect a series
resistor at the output to provide stable operation when driving a high capacitive load. With a 3.3
series resistor,
a capacitive load of 10 nF can be driven, which is usually sufficient for typical LCD applications.
Copyright 2009–2011, Texas Instruments Incorporated
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